Nishi Compare · capabilities, evidence and delivery

Comparison

Compare capabilities and delivery evidence. Source discovery, qualification, deployment and accepted outcomes are separate; an open contract names work still to verify.

Overview

The purpose, declared position and evidence coverage of this domain. Source presence and completed acceptance are different measures.

Where we are. MEASURED 2026-09-03, and the finding is an ADOPTION gap, not a build gap. The estate already holds FOURTEEN codegen backends as real C in nxc2 (aarch64 armv7a cortex_m gcn loongarch64 metal mips64 ppc64le ptx riscv riscv32 s390x wasm x86_64, 10 to 80 KB each, not stubs) and TEN sovereign ISA emulators written in NishiLang (rv64 arm64 armv7a cortexm loongarch64 mips64 ppc64le riscv32 s390x sparc64, plus x86 real-mode and stage2 tests). nx_catalog says all ten emulators are SOURCE-ONLY: 0 built, 0 promoted, 0 registered, 0 invoked -- roughly 60 KB of the exact published-emulator capability the operator asked for, dark. ONE of the ten had a KAT (rv64); the only differential proof in the estate was bench/gate_nx_emu_diff.sh, a shell script needing WSL plus riscv64 binutils plus qemu in order to judge, which judges in shell. nx_ribosome seals a 15-target enum whose own header calls the SILICON_HDL emit target a stub. nx_nxeconform_gate, the conformance gate for our OWN executable format, is PROMOTED-UNREGISTERED: a real 77 KB binary nobody can call. There was no ISA domain among the 101 compare domains, no ISA census, and no cross-ISA conformance organ.

Where we are. WHAT THE FIRST RUN OF THE RULER MEASURED (nx_isa_conform_gate, in process, KATs encoded from the ISA manuals): rv64 5 of 6 instruction classes, mips64 4 of 5, archs_measured 2 of 10. That is the first time eight of these emulators have been measured at all, and the first number this domain has ever had.

Where we need to go. OPERATOR 2026-09-03: have NishiLang work on ALL the hardware backends, ISAs and microarchitectures -- mainstream, Chinese sovereign, open, FPGA soft-core and synthesis, GPU, AI accelerator, DSP, MCU, legacy and bytecode -- keep them IN SYNC, add our own September-2026-grounded Nishi architecture, so that when we deploy a capability it works across all these systems, with PROOF via our own Nishi emulator that is PUBLISHED AND SEEABLE. Two operator rulings the same day: (1) prove the RULER first and widen behind it, rather than chasing reach; (2) the 14 C backends are ORACLE-ONLY -- reference implementations to diff against, never in the build path, because building them needs gcc or clang and that is a third party in the build path.

Where we need to go. OPERATOR 2026-09-03, RAISING THE BAR: "LLVM and GCC emit for more machines and will for a while -- i want to EXCEED this on our /compare and we want to be the MOST COMPREHENSIVE with a system from the first byte up to work with new ISAs easily, syncing our capabilities to them and optimizing to their opportunities." Accepted, and it changes the axis rather than the ambition. Target COUNT is an OUTPUT; the input is what ONE NEW TARGET COSTS. In the field a new machine is a hand-written backend -- LLVM: instruction selection, register allocation hooks, calling convention, scheduling model, assembly printer, disassembler, object writer, tens of thousands of lines of C++ even with TableGen; GCC: a machine description plus target macros plus target hooks, with the pipeline description as the long pole; QEMU: a hand-written TCG frontend that buys EXECUTION only and never emission. All three are engineer-months per machine, which is precisely why their target lists grow slowly and why ours can overtake them.

Where we need to go. THE NISHI ANSWER, AND IT IS THE WHOLE ARCHITECTURE: AN ISA IS A DATA DECLARATION AND EVERYTHING ELSE IS GENERATED FROM IT. One spec table per machine -- encodings, operand forms, register file, endianness, address width, calling convention, available extensions -- and from that ONE table we generate the encoder, the emulator that decodes exactly what the encoder emits, the conformance KATs that prove the two agree, and the optimizer's view of that machine's OPPORTUNITIES (vector width, addressing modes, fused forms, atomics). The seed is not hypothetical: nx_isa_spec.nx is already a SPEC-DRIVEN multi-arch encoder whose own header calls itself "the capability that removes the last hand-written piece of the machine-code generator". Three consequences, each a measurable exceed with its own done-rule: (1) COST PER NEW TARGET -- rows of data against a backend's LOC, proven by taking a NEW ISA from nothing to emit plus emulate plus conformance-green in ONE session; (2) CROSS-ISA BIT-IDENTICAL EXECUTION as a refusing gate, which no field stack offers -- LLVM and GCC guarantee nothing of the kind (floating point, UB and target-dependent lowering each break it), QEMU is an oracle for one ISA at a time and never compares across them, and WASI gets portability by having exactly ONE machine, which is the opposite of proving that N machines agree; (3) ENCODER AND DECODER FROM ONE SOURCE OF TRUTH, so the assembler and the emulator cannot drift the way separately-written ones always do. Reach then follows: once a machine costs a declaration, the 122-row population is a WORKLIST rather than an aspiration.

The unit. 1 u = one measured session-leg (organ plus gate plus live flip), the standing calibration.

Research bar. LLVM target set is measured on the reference multi-target backend collection: AArch64, AMDGPU, ARM, AVR, BPF, Hexagon, Lanai, LoongArch, MIPS, MSP430, NVPTX, PowerPC, RISCV, SPARC, SPIRV, SystemZ, VE, WebAssembly, X86, XCore [@llvmtargets]. Theirs: PINNED isa.refs llvmtargets. Ours: ours emits for 3 targets in the sovereign lane and holds 14 more as C oracles; LLVM wins reach and does not gate on cross-target agreement.

Research bar. GCC back ends is measured on the GCC per-target back-end table with its scheduling and pipeline description status per machine [@gccbackends]. Theirs: PINNED isa.refs gccbackends. Ours: GCC reaches machines nobody else does (m68k, s390, VAX, SuperH, AVR); same absence of a cross-target determinism guarantee.

Research bar. QEMU emulated targets is measured on the reference multi-ISA emulator: the machines it can execute and boot [@qemu]. Theirs: PINNED isa.refs qemu. Ours: ours executes 10 ISAs in process with no dependency; QEMU executes far more and is our differential ORACLE, never a runtime or build dependency.

Research bar. WebAssembly plus WASI is measured on portability by defining ONE machine and moving every host to it: the core spec plus the system interface [@wasmspec]. Theirs: PINNED isa.refs wasmspec. Ours: the honest rival philosophy: one machine everywhere vs N machines proven to agree. We ship both doors.

Latest recorded release

2026-09-03 · ISA5

RULE 3 NOW REPORTS EVERY SITE, NOT ONE PER FILE, AND IS BITE-PROVEN IN BOTH DIRECTIONS. Added sl_next_line and a resume argument so the scan continues past each hit; the caller loops until the rule returns -1. BITE, on the real corpus rather than a fixture: reverting ONE already-fixed line in nx_palette_test.nx to its defective form made the rule fire and name nx_palette_test.nx:74 exactly; restoring the fix made it silent again across 19242 files. Both directions measured, mutation reverted and verified reverted. DECLARED LIMIT, written into the source: the resume is line-granular, so a single line carrying TWO such sites reports only the first -- measured on this tree every offending line carried exactly one, so the floor and the value coincide here, but it is a floor and it is named as one.

Release history and work log

Release entries describe recorded changes; they do not establish that every capability passed evaluation.

25 of 47 capability source symbols found|3 of them authored stronger-claims|22 open|coverage 531/1000|adoption 8 full / 17 partial

Evidence profile — what the gaps on this board actually are

Unstamped. No evidence profile is published for this domain yet: run nx_swcompare_evidence isa and this section fills itself on the next beat. No numbers are shown, deliberately — a zero-filled profile would read as a board with no gaps, which is the one wrong answer nobody would question.

Production map

Follow the dependencies, declared acceptance criteria and recorded priorities. Inspect source binding before treating a rank as executable work.

Ranking source binding: UNAVAILABLE. Recorded priorities require current acceptance evidence and resource checks before execution.

Recorded ranking withheld

Current prerequisite graph is invalid or unavailable. Historical rank data is retained, but cannot establish a current order. Latest execution outcome is unverified.

Declared roadmap — contract, acceptance, executor, effort

Rung	Closes with	Definition of done (pre-declared)	Executor	Est.
M0 (ISA1) after 1u	DONE	the ISA population as published data	knowledge/isa_targets.conf	isa_targets_conf u
M0 (ISA2) after 2u	DONE	the conformance ruler: in-process, manual-derived KATs, five-way outcomes, per-arch ratchet, worklist printed last	runtime/nx_isa_conform_gate.nx	ic_classify u
M1 (ISA3) after 1u	OPEN	build, promote and register the six emulator CLIs that already have mains	runtime/nx_emu_rv64_main.nx	_ABSENT_:isa_emu_six_registered u
M1 (ISA4) after 2u	OPEN	ELF loader plus CLI for the four lib-only emulators	runtime/nx_emu_armv7a.nx	_ABSENT_:emu_armv7a_load_elf u
M1 (ISA5) after 1u	OPEN	MIPS64 conditional branches with correct delay-slot semantics	runtime/nx_emu_mips64.nx	_ABSENT_:mi_branch_cond u
M1 (ISA6) after 0.5u	OPEN	MIPS64 DSRL and DSRA must differ	runtime/nx_emu_mips64.nx	_ABSENT_:mi_shift_arith u
M1 (ISA7) after 0.5u	OPEN	MIPS64 ADDIU must be a 32-bit op sign-extended to 64	runtime/nx_emu_mips64.nx	_ABSENT_:mi_addiu_w u
M1 (ISA8) after 1u	OPEN	the step budget must be its own named outcome in every emulator	runtime/nx_emu_mips64.nx	_ABSENT_:mi_step_budget_named u
M1 (ISA9) after 1u	OPEN	KAT block: AArch64	runtime/nx_isa_conform_gate.nx	_ABSENT_:ic_arm64_imm_arith u
M1 (ISA10) after 1u	OPEN	KAT block: Cortex-M Thumb	runtime/nx_isa_conform_gate.nx	_ABSENT_:ic_cortexm_imm_arith u
M1 (ISA11) after 0.5u	OPEN	KAT block: RISC-V RV32	runtime/nx_isa_conform_gate.nx	_ABSENT_:ic_riscv32_imm_arith u
M1 (ISA12) after 1u	OPEN	KAT block: PowerPC64 LE	runtime/nx_isa_conform_gate.nx	_ABSENT_:ic_ppc64le_imm_arith u
M1 (ISA13) after 1u	OPEN	KAT block: LoongArch64	runtime/nx_isa_conform_gate.nx	_ABSENT_:ic_loongarch64_imm_arith u
M1 (ISA14) after 1u	OPEN	KAT block: IBM z/Architecture	runtime/nx_isa_conform_gate.nx	_ABSENT_:ic_s390x_imm_arith u
M1 (ISA15) after 1u	OPEN	KAT block: SPARC64	runtime/nx_isa_conform_gate.nx	_ABSENT_:ic_sparc64_imm_arith u
M1 (ISA16) after 1u	OPEN	KAT block: ARMv7-A	runtime/nx_isa_conform_gate.nx	_ABSENT_:ic_armv7a_imm_arith u
M2 (ISA17) after 2u	OPEN	the differential oracle as an ORGAN, replacing the shell harness	runtime/nx_isa_oracle_diff.nx	_ABSENT_:iod_run_corpus u
M2 (ISA18) after 3u	OPEN	CROSS-ISA BIT-IDENTICAL EXECUTION as a refusing gate -- THE EXCEED	runtime/nx_isa_determinism_gate.nx	_ABSENT_:rk_isa_determinism u
M2 (ISA19) after 2u	OPEN	sovereign AArch64 emitter wired to a target census	runtime/nxasm_arm64_enc.nx	_ABSENT_:a64_isa_row u
M2 (ISA20) after 1u	OPEN	wasm64 memory64 door	runtime/nx_compile_wat.nx	_ABSENT_:cw_memory64 u
M3 (ISA21) after 3u	OPEN	NX-ISA as a SPEC TABLE, with encoder, emulator and conformance generated from it	runtime/_hdl_build/nx_isa_spec.nx	_ABSENT_:isa_nx_spec_rows u
M3 (ISA22) after 0.5u	OPEN	register nx_nxeconform_gate so our own executable format is checkable	runtime/nx_nxeconform_gate.nx	_ABSENT_:nxeconform_registered u
M3 (ISA23) after 3u	OPEN	de-stub the silicon HDL emit target	runtime/nx_ribosome.nx	_ABSENT_:nx_hdl_emit u
M3 (ISA24) after 1u	OPEN	the ribosome cost model must be MEASURED, not guessed	runtime/nx_ribosome.nx	_ABSENT_:nx_ribosome_cost_measured u
M4 (ISA25) after 1u	OPEN	declare the 14 C backends ORACLE-ONLY and fence them out of the build path	knowledge/isa_targets.conf	_ABSENT_:isa_oracle_only_decl u
M5 (ISA26) after 2u	OPEN	the published, watchable emulator surface	runtime/nx_emu_rv64_main.nx	_ABSENT_:isa_emu_page u
M6 (ISA27) after 3u	OPEN	the ISA SPEC TABLE schema: one declaration per machine covering encodings, operand forms, register file, endianness, address width, calling convention and extensions	runtime/_hdl_build/nx_isa_spec.nx	_ABSENT_:isa_spec_target_rows u
M6 (ISA28) after 3u	OPEN	GENERATE THE DECODER from the same table the encoder reads	runtime/nx_isa_determinism_gate.nx	_ABSENT_:isa_spec_decoder_gen u
M6 (ISA29) after 2u	OPEN	GENERATE THE CONFORMANCE KATS from the same table	runtime/nx_isa_conform_gate.nx	_ABSENT_:isa_spec_kat_gen u
M6 (ISA30) after 2u	OPEN	PER-ISA OPPORTUNITY MODEL read from the declaration, not hand-tuned	runtime/nx_ribosome.nx	_ABSENT_:isa_opportunity_rows u
M6 (ISA31) after 3u	OPEN	TIME-TO-NEW-TARGET measured end to end on a machine we have never emitted for	knowledge/isa_targets.conf	_ABSENT_:isa_newtarget_cost u

Ladder verdict. NOT DECLARED. This board names no dated best-in-class or frontier target and no rung roles (sotatarget and rungrole rows on its plan); the ranker labels it NO-LADDER until it does, and until then its rungs climb toward a target nobody has written down. Bars read NO-BAR against the current month 2026-10.

Bar freshness, counted
Class	Count	Note
bars	0	sotabar rows on the plan
fresh	0	the bar month is the current month
attested	0	an older bar with a this-month barscan reporting no newer entry
stale	0	a this-month scan saw a newer month the bar ignores
unattested	0	nobody looked this month
malformed	0	a sotabar row missing a field
duplicate	0	bar ids an earlier row already carries
bars, summed	0	RECONCILED: the parts sum to the total 0
current month	2026-10	the month every bar is judged against

Treatment verdict. NOT DECLARED. No rung on this board declares its three-step treatment (a treat row naming the MCP row, the API route, the primitive it composes, the workflow that composes it and the agent beat that runs it); the ranker labels every rung TREATMENT-UNDECLARED until it does.

Inspect a rung and its prerequisites

Declared nodes 31. Rank input binding: UNAVAILABLE. Dependency order is authored. Implementation, acceptance evidence, authority and resource readiness are unverified. No action is recommended or dispatched here.

Plan SHA-256 3abee65bac7bdd9219e397cd9d47b79811c96fcf8edb0e037067b625f09888f2. Target rows 0; role rows 0. Existing risks and release worklog retain their own scope; no node completion is inferred.

Invalid declared graph. Malformed rows or IDs 31; duplicate IDs 0; duplicate prerequisites 0; missing prerequisites 0; cyclic or cycle-dependent nodes 0. Node paths withheld.

Learning and practice paths

No structured learning path is declared for this plan. Existing research, roadmap and worklog remain available above.

Rung dossiers — every record that bears on a rung, in one place

Joined by symbol, never typed. Each dossier is assembled on every publish from the rows this board already carries: the plan's rung row, the matrix row that carries its contract symbol (its status re-measured by the one symbol ruler), the gate the organ declares and the verdict the evidence referee recorded on its last run, the reference marks in the rung text, the design rows that name the rung and the work log filed against it. The capability matrix links each cell to its dossier and each dossier links back to its cell and forward to the rungs it stands on; a dependency naming no rung on this plan is written as UNRESOLVED rather than linked. Absences are named: NO-MATRIX-ROW, NO-GATE-DECLARED, UNRECORDED.

Gate verdicts: UNSTAMPED — no per-gate verdict artifact is published for this domain yet (nx_swcompare_evidence isa writes it beside its stamp); every gate below reads UNRECORDED until it runs.

Gate declarations: knowledge/organ_gate.conf read from this working directory (1 rows) and from the estate root (196 rows); rows in both counted once: 0; declarations read: 197. Every declaration in either copy counts, so a stub beside the publisher can never hide the root.

ISA1 M0 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`DONE` · executor knowledge/isa_targets.conf · isa_targets_conf u · stands on 1u (UNRESOLVED: no such rung on this plan)
Definition of done	the ISA population as published data
Matrix cell	NO-MATRIX-ROW — no matrix row carries `DONE`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	2026-09-03 measure nx_catalog over the ten emulators: all SOURCE-ONLY, 0 built 0 promoted 0 registered 0 invoked. 6 have _main CLIs, 4 are lib-only. Helper names do not collide across all ten, so one gate can import them all. 2026-09-03 measure nx_capsearch over 7250 candidates ranked nx_isa_spec.nx first: a spec-driven multi-arch instruction encoder already exists. It is ABSENT from the laptop tree, so laptop and NAS have forked here. 2026-09-03 land knowledge/isa_targets.conf written, 12059 B verified on disk: the operator's brief plus roughly 40 ISAs it did not name, with impl and ext as separate classes.

ISA2 M0 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`DONE` · executor runtime/nx_isa_conform_gate.nx · ic_classify u · stands on 2u (UNRESOLVED: no such rung on this plan)
Definition of done	the conformance ruler: in-process, manual-derived KATs, five-way outcomes, per-arch ratchet, worklist printed last
Matrix cell	NO-MATRIX-ROW — no matrix row carries `DONE`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	2026-09-03 land nx_isa_conform_gate.nx uploaded through the chunked content-put lane, sha 4213cf5c, and BUILT first try at 60976 B with src_sha256 equal to the upload receipt -- the bytes compiled are provably the bytes authored. 2026-09-03 measure first run: rv64 5/6, mips64 4/5, 16 of 17 teeth, verdict RED, ratchet seeded 16 B. nx_organ_ship correctly REFUSED to promote a red gate. Coverage published as a number rather than a verdict, exactly as designed. 2026-09-03 retract the organ's own header claimed neither emulator can return -2. FALSE: nx_emu_rv64.nx defines EMU_RV_RANOFF = -2 and uses it as the initial value of result. Treating it as WRONG-ANSWER would report a structural non-completion as an arithmetic disagreement -- the exact defect this organ refuses, committed inside it. Fixed to a fifth named outcome and the header carries the correction. 2026-09-03 lesson the build was REFUSED by nx_magicratchet for ADDING one inline literal (a 1792 buffer guard). The refusal was right. Fixed by DERIVING the bound from the buffer size and a named longest-row constant rather than renaming the literal. A constant named for its value is still a magic number. 2026-09-03 lesson MCP nx_fs returned "Unable to connect" twice while the estate was healthy. Varying the CLIENT (nxmcp.py over :443) reached the server immediately and revealed the real answer, which was the magic-ratchet refusal. A repeated identical failure is evidence of a shared cause, and the client is shared too. 2026-09-03 land nx_isa_conform_gate GREEN 20/20, exit_code 0, NONPASS none. The ruler binds: a regression in either measured ISA fails the gate, and the eight unmeasured arches are named in its own output every run. 2026-09-03 lesson A refused build DESTROYED the _build fossil: nx_catalog read BUILT yes 62608 B before an admission refusal and BUILT NO after, while the STAGED artifact survived and promoted cleanly. Any drift instrument comparing against buildroot/_build is silently re-baselined by a refusal. 2026-09-03 land nx_isa_conform_gate PROMOTED 62616 B and REGISTERED. The first run of the live gate named its own failing KAT: rv64.shift-logical got=255 want=15 WRONG-ANSWER.

ISA3 M1 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_emu_rv64_main.nx · _ABSENT_:isa_emu_six_registered u · stands on 1u (UNRESOLVED: no such rung on this plan)
Definition of done	build, promote and register the six emulator CLIs that already have mains
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA4 M1 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_emu_armv7a.nx · _ABSENT_:emu_armv7a_load_elf u · stands on 2u (UNRESOLVED: no such rung on this plan)
Definition of done	ELF loader plus CLI for the four lib-only emulators
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA5 M1 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_emu_mips64.nx · _ABSENT_:mi_branch_cond u · stands on 1u (UNRESOLVED: no such rung on this plan)
Definition of done	MIPS64 conditional branches with correct delay-slot semantics
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	2026-09-03 measure THE RULER FOUND A REAL DEFECT IN THE SOVEREIGN RV64 INTERPRETER ON ITS FIRST RUN. nx_emu_rv64.nx:163 read: if (w >> 30) & 1 == 0. In this dialect == binds TIGHTER than &, so that parses as (w>>30) & (1==0) = 0, ALWAYS FALSE, and every SRLI silently took the SRAI path. Invisible for non-negative values, which is why the pre-existing positive-only rv64 test never saw it. The 32-bit twin on line 218 has had the parentheses all along: a fix present in one verb and absent from its sibling. 2026-09-03 land Fixed with parentheses, proven by the instrument that found it: rv64 5/6 to 6/6, ratchet TIGHTENED base=5 now=6, the correct polarity for a good-when-higher metric. 2026-09-03 measure Estate-wide census of that precedence shape over buildroot/runtime, corpus_complete=1 across 23520 files: and-1-eq-1 four code sites ALL ACCIDENTALLY CORRECT because 1==1 is 1; and-7-eq-0 two sites both inside COMMENTS; and-0xff-eq zero; and-255-eq ONE site, nx_crypsis_test.nx:29, a REAL defect comparing a single BIT instead of a byte. Two real defects, four fragile-but-correct sites, two comments. Both real ones fixed. 2026-09-03 land MIPS64 conditional branches BEQ BNE BLEZ BGTZ BLTZ BGEZ implemented with the delay slot honoured (target = npc + offset shifted 2, delay-slot instruction always executes). Before this the interpreter could not run a LOOP, so we-emulate-MIPS64 was not a true claim. 2026-09-03 measure All three MIPS64 fixes PROVEN by KATs that can actually discriminate: shift-logical-vs-arith needs a DOUBLE shift by 31 because MIPS encodes the shift amount in five bits and one shift by 31 leaves the same low byte under both shifts; addiu-is-32-bit needs the high bits shifted back down because truncation to 32 bits never changes the low byte. coverage rv64 6/6, mips64 7/7, ratchet mips64 4 to 7. 2026-09-03 land THE PRECEDENCE HAZARD GOT ITS BUS STOP, AND THEN GOT UNWIRED FOR CAUSE. nx_srclint -- the estate lint whose own header says the fifth hand-fix proves the fix belongs in a linter -- was itself BUILT-UNPROMOTED and dark. It is now PROMOTED and REGISTERED (rules 1 and 2 adopted, 19222-file corpus). RULE 3 for the bitwise-vs-comparison trap was written, built and measured: first draft 212 files on the whole corpus, and READING the hits named three false-positive buckets the naive scan could not see -- semicolon-separated statements, a and inside a STRING LITERAL, and separate function arguments. A second draft handling all three STILL reported 212 with a plainly-correct file among them, and the rule does not print its offset so its output cannot be adjudicated without re-deriving every hit by hand. So rule 3 is DELIBERATELY NOT WIRED, with the function, the 212 measurement and the three buckets kept in source as the spec for finishing it. A detector with false positives is worse than none -- that is this organ own standard, and shipping the rule wired would have broken the standard the organ exists to hold. 2026-09-03 land THE PRECEDENCE BUS STOP IS BUILT, PROVEN AND WIRED, AND THE DEFECT CLASS IS EXTINCT. nx_srclint RULE 3 now runs BY DEFAULT and sits in the name-set ratchet, so any new occurrence fails the lint. Final measurement: 0 hits across 19236 files. Draining it took five passes because the rule reports one hit per FILE: 24 then 14 then 12 then 8 then 5 then 4 then 2 then 0, roughly 70 sites fixed in total. WHAT IT CAUGHT, all real: nx_parallel_run masked a child EXIT STATUS down to bit 0; nx_capability_no_regression_check tested and-2-eq-2, i.e. THE WRONG BIT, inside a regression detector; nx_f32_log_test and nx_f32_activations_test each asserted and-1-neq-1, which is x-and-0 and can NEVER fire -- two vacuous tests; and roughly sixty byte-comparison assertions across the codec, css, layout, palette, tls and crypto suites compared ONE BIT instead of a whole byte, which made those assertions nearly unfalsifiable. 2026-09-03 retract I PUBLISHED A ZERO THAT WAS A FALSE CLEAN AND CAUGHT IT ONLY BY WIRING THE RULE. Mid-drain I measured 0 remaining and said the class was extinct. It was not: the run had been launched as nx_job_run nx_srclint OUT --rule3, and the flag WAS NOT FORWARDED to the organ, so rule 3 never executed and 0 meant DID-NOT-RUN, not CLEAN. Wiring the rule on by default immediately showed 12. A ZERO FROM AN OPT-IN CHECK IS ONLY EVIDENCE IF YOU PROVED THE OPT-IN ARRIVED -- the same shape as a gate that passes because its fixture never reached the condition, and the reason this organ demands a planted positive before believing any clean run. 2026-09-03 lesson A RULE THAT REPORTS ONE HIT PER FILE UNDER-REPORTS A POPULATION AND TURNS A SWEEP INTO A SERIES OF PASSES. Each drain pass revealed the next instance in the same files, which is why the count fell 24-14-12-8-5-4-2-0 instead of going to zero once. The rule is honest but its GRANULARITY is the worklist defect one level down: it should report every site, not the first. Filed as the next improvement to rule 3 rather than left implicit. 2026-09-03 land RULE 3 NOW REPORTS EVERY SITE, NOT ONE PER FILE, AND IS BITE-PROVEN IN BOTH DIRECTIONS. Added sl_next_line and a resume argument so the scan continues past each hit; the caller loops until the rule returns -1. BITE, on the real corpus rather than a fixture: reverting ONE already-fixed line in nx_palette_test.nx to its defective form made the rule fire and name nx_palette_test.nx:74 exactly; restoring the fix made it silent again across 19242 files. Both directions measured, mutation reverted and verified reverted. DECLARED LIMIT, written into the source: the resume is line-granular, so a single line carrying TWO such sites reports only the first -- measured on this tree every offending line carried exactly one, so the floor and the value coincide here, but it is a floor and it is named as one. 2026-09-03 lesson A PLANT THAT THE HARNESS NEVER READ IS NOT A PLANT. The first bite attempt wrote a fixture with three obvious defects to /tmp and ran the lint with --dir at it; the lint answered corpus=1 files, 0 sources and no hits. That reads exactly like a dead rule, and it is not -- the organ never READ the file, so nothing was tested in either direction. The bite that actually proved anything mutated a file already inside the real corpus the organ scans. ASSERT THE FIXTURE WAS REACHED BEFORE READING ITS VERDICT: 0 sources is the tell, and it sits in the same output as the verdict that would otherwise have been believed.

ISA6 M1 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_emu_mips64.nx · _ABSENT_:mi_shift_arith u · stands on 0.5u (UNRESOLVED: no such rung on this plan)
Definition of done	MIPS64 DSRL and DSRA must differ
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	2026-09-03 land MIPS64 DSRL made LOGICAL via a new mi_srl mask helper. DSRL and DSRA had been the SAME expression, so one of the two was necessarily wrong. 2026-09-03 lesson Two edits fired concurrently at the SAME file: one landed, the other was SILENTLY CLOBBERED, and BOTH returned OK. Caught only by grepping for each new form afterwards. Sequential edits from then on.

ISA7 M1 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_emu_mips64.nx · _ABSENT_:mi_addiu_w u · stands on 0.5u (UNRESOLVED: no such rung on this plan)
Definition of done	MIPS64 ADDIU must be a 32-bit op sign-extended to 64
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	2026-09-03 land MIPS64 ADDIU made a 32-bit op sign-extended to 64 via a new mi_sx32 helper. ADDIU and DADDIU had shared one code path and were indistinguishable.

ISA8 M1 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_emu_mips64.nx · _ABSENT_:mi_step_budget_named u · stands on 1u (UNRESOLVED: no such rung on this plan)
Definition of done	the step budget must be its own named outcome in every emulator
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA9 M1 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_isa_conform_gate.nx · _ABSENT_:ic_arm64_imm_arith u · stands on 1u (UNRESOLVED: no such rung on this plan)
Definition of done	KAT block: AArch64
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	2026-09-03 land AArch64 KAT block landed and PASSED 4 of 4 on its FIRST measurement: imm-arith, movk-keeps-lanes, madd, cbz-taken, encoded from the Arm ARM. The largest emulator in the set at 18 KB had never been measured at all. Gate 25/25 GREEN, ratchet seeds arm64 at 4, coverage rv64 6/6 mips64 7/7 arm64 4/4, archs_measured 3 of 10.

ISA10 M1 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_isa_conform_gate.nx · _ABSENT_:ic_cortexm_imm_arith u · stands on 1u (UNRESOLVED: no such rung on this plan)
Definition of done	KAT block: Cortex-M Thumb
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA11 M1 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_isa_conform_gate.nx · _ABSENT_:ic_riscv32_imm_arith u · stands on 0.5u (UNRESOLVED: no such rung on this plan)
Definition of done	KAT block: RISC-V RV32
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	2026-09-03 land RV32 CONDITIONAL BRANCHES IMPLEMENTED, AND RISCV32 MEASURED 6/6 ON ITS FIRST RUN. Reading the decoder showed opcode 0x63 was entirely absent -- the same gap the ruler had named in mips64 hours earlier -- so RV32 could not run a LOOP and "we emulate RV32" was not yet a true claim. Added the full B-type family (beq bne blt bge bltu bgeu) mirroring the RV64 sibling, with the signed forms comparing SIGN-EXTENDED 32-bit values and the unsigned forms comparing the raw masked values, and the 13-bit offset decoded through named constants rather than inline literals. PROVEN by a KAT that could not have passed before it: riscv32.branch-loop got=45 want=45, a sum 0..9 driven by a bne back-branch. Six KATs green: imm-arith, sub, logic, mul, load-store, branch-loop. Gate 32/32 GREEN, ratchet seeds riscv32 at 6, coverage rv64 6/6 mips64 7/7 arm64 4/4 riscv32 6/6, archs_measured 4 of 10. 2026-09-03 lesson RV32I SHARES ITS BASE ENCODING WITH RV64I, SO FIVE OF THE SIX KAT WORD SEQUENCES ARE BYTE-IDENTICAL TO THE RV64 BLOCK. That makes riscv32 the cheapest arch on the board to measure and it is why it was taken next -- but it also means a shared-encoding arch can INHERIT a fixture bug as easily as a fixture. The words reused here are the ones already oracle-verified against riscv64-as and qemu, so the inheritance is of PROVEN bytes, not of assumptions.

ISA12 M1 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_isa_conform_gate.nx · _ABSENT_:ic_ppc64le_imm_arith u · stands on 1u (UNRESOLVED: no such rung on this plan)
Definition of done	KAT block: PowerPC64 LE
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA13 M1 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_isa_conform_gate.nx · _ABSENT_:ic_loongarch64_imm_arith u · stands on 1u (UNRESOLVED: no such rung on this plan)
Definition of done	KAT block: LoongArch64
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA14 M1 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_isa_conform_gate.nx · _ABSENT_:ic_s390x_imm_arith u · stands on 1u (UNRESOLVED: no such rung on this plan)
Definition of done	KAT block: IBM z/Architecture
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA15 M1 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_isa_conform_gate.nx · _ABSENT_:ic_sparc64_imm_arith u · stands on 1u (UNRESOLVED: no such rung on this plan)
Definition of done	KAT block: SPARC64
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA16 M1 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_isa_conform_gate.nx · _ABSENT_:ic_armv7a_imm_arith u · stands on 1u (UNRESOLVED: no such rung on this plan)
Definition of done	KAT block: ARMv7-A
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA17 M2 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_isa_oracle_diff.nx · _ABSENT_:iod_run_corpus u · stands on 2u (UNRESOLVED: no such rung on this plan)
Definition of done	the differential oracle as an ORGAN, replacing the shell harness
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA18 M2 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_isa_determinism_gate.nx · _ABSENT_:rk_isa_determinism u · stands on 3u (UNRESOLVED: no such rung on this plan)
Definition of done	CROSS-ISA BIT-IDENTICAL EXECUTION as a refusing gate -- THE EXCEED
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA19 M2 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nxasm_arm64_enc.nx · _ABSENT_:a64_isa_row u · stands on 2u (UNRESOLVED: no such rung on this plan)
Definition of done	sovereign AArch64 emitter wired to a target census
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA20 M2 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_compile_wat.nx · _ABSENT_:cw_memory64 u · stands on 1u (UNRESOLVED: no such rung on this plan)
Definition of done	wasm64 memory64 door
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA21 M3 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/_hdl_build/nx_isa_spec.nx · _ABSENT_:isa_nx_spec_rows u · stands on 3u (UNRESOLVED: no such rung on this plan)
Definition of done	NX-ISA as a SPEC TABLE, with encoder, emulator and conformance generated from it
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA22 M3 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_nxeconform_gate.nx · _ABSENT_:nxeconform_registered u · stands on 0.5u (UNRESOLVED: no such rung on this plan)
Definition of done	register nx_nxeconform_gate so our own executable format is checkable
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	2026-09-03 land nx_nxeconform_gate registered and authorised: PROMOTED-UNREGISTERED to REGISTERED. Our own executable format finally has a callable conformance gate.

ISA23 M3 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_ribosome.nx · _ABSENT_:nx_hdl_emit u · stands on 3u (UNRESOLVED: no such rung on this plan)
Definition of done	de-stub the silicon HDL emit target
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA24 M3 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_ribosome.nx · _ABSENT_:nx_ribosome_cost_measured u · stands on 1u (UNRESOLVED: no such rung on this plan)
Definition of done	the ribosome cost model must be MEASURED, not guessed
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA25 M4 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor knowledge/isa_targets.conf · _ABSENT_:isa_oracle_only_decl u · stands on 1u (UNRESOLVED: no such rung on this plan)
Definition of done	declare the 14 C backends ORACLE-ONLY and fence them out of the build path
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA26 M5 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_emu_rv64_main.nx · _ABSENT_:isa_emu_page u · stands on 2u (UNRESOLVED: no such rung on this plan)
Definition of done	the published, watchable emulator surface
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	2026-09-03 measure THE /compare 404 IS AN EDGE OUTAGE, NOT A PUBLISHING BUG, AND THE ORIGIN IS HEALTHY. Measured both sides the same minute: via loopback with correct SNI, sites.elf answers 200 for /compare/isa and 401 for /gallery (alive, auth-gated); via the public edge /compare /gallery /hub /studio ALL answer 404 while / and /video/ answer 200. The 404 body carries the nginx signature, so DSM nginx fronts the sovereign stack and serves a DIFFERENT docroot (the apex links /pages and /posts, absent from sites/nishifamily, and emits X-Nishi-Surface nishipages-apex). The compare gateway was PROVEN innocent: nx_http_probe on loopback 18102 returns 200 for /compare/gpu 106681 B and /compare/isa 89991 B. Filed as debt 1788459203, superseding a July DOES-NOT-REPRODUCE correction and giving open D008 its concrete manifestation. Fix is operator/infra: nginx config lives in the OS namespace the sovereign writer denies by construction. 2026-09-03 lesson I named a cause twice before I had one -- a CMS shadowing the docroot, then a dead supervisor -- and both were retracted from evidence. The second came from reading absence in nx_services as death when nx_services reads a PORTMAP, not the process table. The probe that actually settled it (nx_http_probe, loopback-only) was one cap mint away the whole time. A 404 is the ABSENCE of a diagnosis and it invites the story you already believe. 2026-09-03 retract /compare/isa IS LIVE AND HAS BEEN. Measured from a TRUE EXTERNAL VANTAGE (laptop, curl over the public internet): 200, 89865 bytes, every emulator row rendering; /compare/gpu 200; /gallery 401 auth-gated; / 200. I RETRACT the edge-outage diagnosis I published earlier today and the debt row that carried it (1788459203, now EATEN, superseded by a correction row). THE FALSE MECHANISM: I claimed DSM nginx fronts the estate and 404s every app route. WHY IT LOOKED TRUE: every probe used nx_https_get, which runs ON THE NAS, so it resolves the domain and connects to :443 LOCALLY -- where DSM nginx does listen -- and never traverses the WAN DNAT. THE TRUE PATH: nx_edge_repoint list shows the GL.iNet redirect https-nas wan:443 DNAT to 192.168.8.240:8443 reflection=1, so WAN already reaches sites.elf. A PORT REACHABILITY IS A PROPERTY OF THE VANTAGE, NOT THE HOST -- the estate has that law written down and I did not apply it. A NAS-side HTTP probe cannot measure the WAN path by construction, so every 404 it returned was TRUE about local :443 and IRRELEVANT to the question asked. RECIPE: public surface = curl from the laptop; origin = nx_https_get with the 127.0.0.1:8443 override and correct SNI. Two vantages, two questions, never interchangeable.

ISA27 M6 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/_hdl_build/nx_isa_spec.nx · _ABSENT_:isa_spec_target_rows u · stands on 3u (UNRESOLVED: no such rung on this plan)
Definition of done	the ISA SPEC TABLE schema: one declaration per machine covering encodings, operand forms, register file, endianness, address width, calling convention and extensions
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA28 M6 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_isa_determinism_gate.nx · _ABSENT_:isa_spec_decoder_gen u · stands on 3u (UNRESOLVED: no such rung on this plan)
Definition of done	GENERATE THE DECODER from the same table the encoder reads
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA29 M6 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_isa_conform_gate.nx · _ABSENT_:isa_spec_kat_gen u · stands on 2u (UNRESOLVED: no such rung on this plan)
Definition of done	GENERATE THE CONFORMANCE KATS from the same table
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA30 M6 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor runtime/nx_ribosome.nx · _ABSENT_:isa_opportunity_rows u · stands on 2u (UNRESOLVED: no such rung on this plan)
Definition of done	PER-ISA OPPORTUNITY MODEL read from the declaration, not hand-tuned
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

ISA31 M6 · cell NO-MATRIX-ROW · gate NO-MATRIX-ROW

Contract	`OPEN` · executor knowledge/isa_targets.conf · _ABSENT_:isa_newtarget_cost u · stands on 3u (UNRESOLVED: no such rung on this plan)
Definition of done	TIME-TO-NEW-TARGET measured end to end on a machine we have never emitted for
Matrix cell	NO-MATRIX-ROW — no matrix row carries `OPEN`; the ranker reads this rung as unmapped and no cell can flip for it. Add the row and the join completes on the next publish.
Gate	the gate join needs a matrix row: no organ is named for this rung
Work log	no log row names this rung yet

dossiers=31 cells_joined=0 no_matrix_row=31 (sum 31) gates_recorded=0 gates_unrecorded=0 no_gate_declared=0 (sum 0 of cells_joined) evgates=UNSTAMPED

Capability comparisons

Compare the field, search individual capabilities and open their source and adoption evidence. Documented presence does not establish comparative quality.

Position map — centrality and distinctiveness

The four-quadrant map the field uses for brand strategy (Dawar and Bagga, HBR June 2015), re-derived from this matrix on every publish. Centrality is the share of the category's feature mass a player covers, each feature weighted by how many hold it; distinctiveness is the average lead over each rival on the rows the player holds; breadth is the depth-weighted share of the whole matrix (the bubble); depth is how deeply the rows held are held; momentum is the day-over-day move off the spine (green rising, red falling, grey until day two); the dashed path runs first day → previous day → today. Dividers are the category means. Axes are fitted to the field of play, so read the tick numerals, not the frame. Rival marks are documented presence, so a rival's position reads the record, never its quality. The picture grades its own readability below; the table beside it is the same data for a screen reader or a second method.

Rows. 47 feature rows mapped of 47 matrix rows; 0 substrate rows (kernels, bounds and instruments the plan's rungrole marks substrate) are the estate's scaffolding, not category features, and stay off the map

Views. 2D cut: centrality, distinctiveness · 3D cube: centrality, distinctiveness, breadth · axes registered: centrality, distinctiveness, breadth, depth, momentum · a board picks its own in knowledge/compare/isa.cdmap (cut|x|y, cube|x|y|z); absent = the HBR defaults

bubble area = breadth · ring = momentum (green rising, red falling, grey until day two) · dashed = category means · axes fitted to the field of play: centrality 100–800, distinctiveness 300–650 of 0–1000 permil (the full range put every player in one corner)
readability of the 2D cut, self-graded by the layout ruler: label overlaps 0 · labels over marks 0 · off-canvas 0 · unresolved labels 0 · mark overlaps 0 (a fact of the data: two players that close are that close) · data spread 686 permil of the plot · quadrant words unseated 0
text contrast, measured with wcag2-ratio (floors from contrast.conf), light theme: labels 16.24 (floor 4.50) · notes 16.24 (floor 4.50) · quadrant words 5.89 (floor 4.50) · tick numerals 5.89 (floor 4.50) · axis titles 5.59 (floor 4.50) · dark theme: labels 13.78 (floor 4.50) · quadrant words 5.55 (floor 4.50) · axis titles 5.97 (floor 4.50) · dark classes under their floor 0 (one figure serves both themes: a dark shortfall is a token to fix, never a class to hide) · classes refused under their floor 0 (a refused class is not drawn; the scale classes are measured, never hidden) · export: SVG PNG (receipt, rendered by the estate's own rasteriser from this page)

axes fitted: centrality 100–800 · distinctiveness 300–650 · breadth 0–500 permil · farther bubbles are painted first, nearer ones over them · the floor shadow is each bubble's (x, y) at height 0
readability of the 3D cube, self-graded by the layout ruler: label overlaps 0 · labels over marks 0 · off-canvas 0 · unresolved labels 0 · mark overlaps 1 (a fact of the data: two players that close are that close) · data spread 192 permil of the plot

Nishi LLVM GCC QEMU WebAssembly+WASI
10 panels over 5 registered axes, every pair once (the lower axis on x, the higher on y) · each panel fitted to its own field of play, first and last tick numerals shown · no labels in a small cut, the legend names the colours; the grade below reports the mark terms only (MM summed over the panels, spread averaged)
readability of the small multiples, self-graded by the layout ruler: label overlaps 0 · labels over marks 0 · off-canvas 0 · unresolved labels 0 · mark overlaps 3 (a fact of the data: two players that close are that close) · data spread 517 permil of the plot

Player	Quadrant	centrality	distinctiveness	breadth	depth	momentum	Rows held	Days on spine	First seen
Nishi	Aspirational	561	610	375	706	0 since 2026-09-23	25	10	2026-09-15
LLVM	Peripheral	383	416	148	777	0 since 2026-09-23	9	10	2026-09-15
GCC	Mainstream	575	375	205	690	0 since 2026-09-23	14	10	2026-09-15
QEMU	Aspirational	684	575	354	793	0 since 2026-09-23	21	10	2026-09-15
WebAssembly+WASI	Peripheral	191	375	63	750	0 since 2026-09-23	4	10	2026-09-15

Day	Matrix rows reviewed	Players recorded
2026-09-15	47	5
2026-09-16	47	5
2026-09-17	47	5
2026-09-18	47	5
2026-09-19	47	5
2026-09-20	47	5
2026-09-21	47	5
2026-09-22	47	5
2026-09-23	47	5
2026-10-08	47	5

How to read this evidence. A Nishi source mark records whether the named symbol is declared in the selected source file. It does not establish working behavior or accepted delivery. A watching tag names an expected source entry; discovering it updates source coverage only. A dark tag means the file exists but the named symbol was not found: inspect the source and contract before assuming the capability is missing or renaming code. Peer codes are authored assessments; unassessed means no comparison is established, not absence. Qualification, deployment identity, runtime observations and acceptance must carry their own evidence. Adoption records the catalog's observed path through source, build, promotion, registration and invocation; libraries use importer evidence and gates use declared execution surfaces. A full catalog path does not establish quality, freshness or a successful user outcome. Partial and unknown states retain their stated next action. Census stamps: importers asof 1790637268, gate census asof 1790104131 (unix seconds; -1 = census absent).

Capability matrix — measured against source

◉ authored stronger claim; source present● present◐ partial○ absent? unassessed; excluded from relative comparison · click any capability for its evidence

Peer cell coverage: authored assessed 188, unassessed 0. Authored assessments are not verified outcomes.

Capability	Nishi	LLVM	GCC	QEMU	WebAssembly+WASI
ISA POPULATION AS DATA (the published denominator) Open — no implementing organ is measured for this axis yet. ~120 rows across 11 classes with impl and ext separated so no ratio can double-count rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them Pros none measured yetCons behind LLVM, GCC, QEMU, WebAssembly+WASI; no implementing organ measured	○	●	●	●	●
ISA CONFORMANCE RULER (KATs from the manuals, in process) Measured: `ic_classify` exists in `runtime/nx_isa_conform_gate.nx`, verified at emit. five-way outcomes: PASS WRONG-ANSWER UNSUPPORTED RAN-OFF-END FAULT -- qemu gives you an exit code and leaves the classification to you rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them Adoption: `GATE:DEPLOYED-DARK trial=-` — PARTIAL: deployed, no execution surface runs it: admit it to the gate roster. not adopted: deployed, no execution surface runs it: admit it to the gate roster Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, QEMU, WebAssembly+WASICons not adopted yet: deployed, no execution surface runs it: admit it to the gate roster	●	○	○	◐	○
FIVE-WAY OUTCOME, NOT PASS/FAIL Source present; authored stronger claim: `ic_outcome_name` in `runtime/nx_isa_conform_gate.nx`, verified at emit. an unimplemented instruction class and a wrong result need OPPOSITE fixes so they must never share a word Adoption: `GATE:DEPLOYED-DARK trial=-` — PARTIAL: deployed, no execution surface runs it: admit it to the gate roster. not adopted: deployed, no execution surface runs it: admit it to the gate roster Pros Source symbol found; stronger capability claim is authored; ahead of LLVM, GCC, QEMU, WebAssembly+WASICons not adopted yet: deployed, no execution surface runs it: admit it to the gate roster	◉	○	○	○	○
PER-ARCH RATCHET (good-when-higher, seeds on first sight) Measured: `ic_ratchet_write` exists in `runtime/nx_isa_conform_gate.nx`, verified at emit. the verdict is no-regression and the coverage is a NUMBER, so the detector never goes permanently red Adoption: `GATE:DEPLOYED-DARK trial=-` — PARTIAL: deployed, no execution surface runs it: admit it to the gate roster. not adopted: deployed, no execution surface runs it: admit it to the gate roster Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, QEMU, WebAssembly+WASICons not adopted yet: deployed, no execution surface runs it: admit it to the gate roster	●	○	○	○	○
NON-PASS WORKLIST PRINTED LAST Measured: `ic_report` exists in `runtime/nx_isa_conform_gate.nx`, verified at emit. a count without a worklist is not actionable, and a worklist in the body is lost to any caller that tails Adoption: `GATE:DEPLOYED-DARK trial=-` — PARTIAL: deployed, no execution surface runs it: admit it to the gate roster. not adopted: deployed, no execution surface runs it: admit it to the gate roster Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, QEMU, WebAssembly+WASICons not adopted yet: deployed, no execution surface runs it: admit it to the gate roster	●	○	○	○	○
MASTER ISA MANAGER, one NAMED state per declared ISA Measured: `im_classify` exists in `runtime/nx_isa_manager.nx`, verified at emit. six states -- MEASURED-GREEN MEASURED-RED GATE-PRESENT-UNRUN EMULATOR-ONLY DECLARED-ONLY NOT-A-TARGET -- decided in ONE function so the counts, the per-row print and the worklist cannot drift apart Adoption: `BUILT-UNPROMOTED` — PARTIAL: compiled, never promoted to the serving root: /api/promote it. not adopted: compiled, never promoted to the serving root: /api/promote it Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, QEMU, WebAssembly+WASICons not adopted yet: compiled, never promoted to the serving root: /api/promote it	●	○	○	○	○
DISCOVERY BY PROBE, NEVER A HARDCODED TARGET LIST Measured: `im_probe_roots` exists in `runtime/nx_isa_manager.nx`, verified at emit. not one architecture name appears in the manager: a new ISA joins by a conf row plus organs named for it, and the id-to-slug exceptions are DATA in knowledge/isa_emu_alias.conf, so adding an ISA never edits the auditor Adoption: `BUILT-UNPROMOTED` — PARTIAL: compiled, never promoted to the serving root: /api/promote it. not adopted: compiled, never promoted to the serving root: /api/promote it Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, QEMU, WebAssembly+WASICons not adopted yet: compiled, never promoted to the serving root: /api/promote it	●	○	○	○	○
COVERAGE RATIOS CARRY THEIR DENOMINATOR, impl AND ext EXCLUDED Measured: `im_is_target` exists in `runtime/nx_isa_manager.nx`, verified at emit. counting a host that implements another row ISA, or an extension, would double-count the base machine; the exclusion is asked in ONE predicate so it cannot be spelled two ways in two places Adoption: `BUILT-UNPROMOTED` — PARTIAL: compiled, never promoted to the serving root: /api/promote it. not adopted: compiled, never promoted to the serving root: /api/promote it Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, QEMU, WebAssembly+WASICons not adopted yet: compiled, never promoted to the serving root: /api/promote it	●	○	○	○	○
THE AUDITOR MUST NOT GO RED BECAUSE AN ISA IS INCOMPLETE Measured: `im_state_meaning` exists in `runtime/nx_isa_manager.nx`, verified at emit. its teeth assert partitions that sum, discovery floors, and by byte-compare that it did not write the ratchets the gates own; a manager gated on ISA health would be red the day it shipped and every day after, and a permanently red detector is one everyone learns to ignore Adoption: `BUILT-UNPROMOTED` — PARTIAL: compiled, never promoted to the serving root: /api/promote it. not adopted: compiled, never promoted to the serving root: /api/promote it Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, QEMU, WebAssembly+WASICons not adopted yet: compiled, never promoted to the serving root: /api/promote it	●	○	○	○	○
EMIT x86-64 DARK — `runtime/nx_compile_x86.nx` EXISTS but does not declare `cx_emit_isa_row`: something shipped at this path under another name, and this mark would read open forever. Repoint the contract to the real entry point (the plan rung AND this row) or rename the function; the flip follows on the next beat, and the `comparewatch-` plane row reads DARK until then. the estate's primary native lane, self-hosting; the row names the census symbol this board needs rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them watching cx_emit_isa_row Pros none measured yetCons behind LLVM (leads), GCC (leads), QEMU; open contract; expected source declaration not established	○	◉	◉	●	○
EMIT RISC-V RV64 DARK — `runtime/nxasm_v2.nx` EXISTS but does not declare `asm_rv64_isa_row`: something shipped at this path under another name, and this mark would read open forever. Repoint the contract to the real entry point (the plan rung AND this row) or rename the function; the flip follows on the next beat, and the `comparewatch-` plane row reads DARK until then. rv64 lowering incl. LN34 lr/sc AMO fence; the watch names the census hook rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them watching asm_rv64_isa_row Pros none measured yetCons behind LLVM (leads), GCC (leads), QEMU; open contract; expected source declaration not established	○	◉	◉	●	○
EMIT WebAssembly wasm32 DARK — `runtime/nx_compile_wat.nx` EXISTS but does not declare `cw_isa_row`: something shipped at this path under another name, and this mark would read open forever. Repoint the contract to the real entry point (the plan rung AND this row) or rename the function; the flip follows on the next beat, and the `comparewatch-` plane row reads DARK until then. threads and shared memory landed LN33; the browser door rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them watching cw_isa_row Pros none measured yetCons behind LLVM, GCC, WebAssembly+WASI (leads); open contract; expected source declaration not established	○	●	◐	○	◉
EMIT AArch64 DARK — `runtime/nxasm_arm64_enc.nx` EXISTS but does not declare `a64_isa_row`: something shipped at this path under another name, and this mark would read open forever. Repoint the contract to the real entry point (the plan rung AND this row) or rename the function; the flip follows on the next beat, and the `comparewatch-` plane row reads DARK until then. an arm64 encoder exists in the assembler and an nx_aarch64 emitter lib exists; neither is wired to a target census rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them watching a64_isa_row Pros none measured yetCons behind LLVM (leads), GCC (leads), QEMU; open contract; expected source declaration not established	○	◉	◉	●	○
EMIT wasm64 memory64 DARK — `runtime/nx_compile_wat.nx` EXISTS but does not declare `cw_memory64`: something shipped at this path under another name, and this mark would read open forever. Repoint the contract to the real entry point (the plan rung AND this row) or rename the function; the flip follows on the next beat, and the `comparewatch-` plane row reads DARK until then. lifts the wasm32 4 GiB wall, the scale-up door for the browser lane rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them watching cw_memory64 Pros none measured yetCons behind LLVM, GCC, WebAssembly+WASI; open contract; expected source declaration not established	○	●	◐	○	●
EMIT Nishi silicon netlist (HDL) DARK — `runtime/nx_ribosome.nx` EXISTS but does not declare `nx_hdl_emit`: something shipped at this path under another name, and this mark would read open forever. Repoint the contract to the real entry point (the plan rung AND this row) or rename the function; the flip follows on the next beat, and the `comparewatch-` plane row reads DARK until then. nx_ribosome seals NX_RBT_SILICON_HDL and its own header calls the emit target a stub -- from the electronics up, this is the last mile watching nx_hdl_emit Pros none measured yetCons open contract; expected source declaration not established	○	○	○	○	○
EMULATE RV64 (interpreter, in process) Measured: `emu_rv64_run_mem` exists in `runtime/nx_emu_rv64.nx`, verified at emit. the most complete of the ten: branches, loads/stores, 6-bit RV64 shifts, muldiv, ecall rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them Adoption: `LIB-WIRED importers=6 nonval=1` — fully adopted (top of its ladder). Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, WebAssembly+WASI; fully adopted on the estate ladderCons behind QEMU (leads)	●	○	○	◉	○
EMULATE MIPS64 big-endian with delay slots Measured: `emu_mips64_run_mem` exists in `runtime/nx_emu_mips64.nx`, verified at emit. PC/nPC model present; NO conditional branch implemented, so it cannot run a loop -- named, not hidden rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them Adoption: `LIB-WIRED importers=2 nonval=1` — fully adopted (top of its ladder). Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, QEMU, WebAssembly+WASI; fully adopted on the estate ladderCons behind GCC (leads)	●	○	◉	○	○
EMULATE AArch64 Measured: `emu_arm64_run_mem` exists in `runtime/nx_emu_arm64.nx`, verified at emit. the largest emulator source at 18 KB and never once measured until this board existed rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them Adoption: `LIB-WIRED importers=6 nonval=1` — fully adopted (top of its ladder). Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, WebAssembly+WASI; fully adopted on the estate ladderCons behind QEMU (leads)	●	○	○	◉	○
EMULATE ARMv7-A Measured: `emu_armv7a_run_mem` exists in `runtime/nx_emu_armv7a.nx`, verified at emit. lib-only: no load_elf and no CLI, so nothing outside a gate can run it rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them Adoption: `LIB-GATE-ONLY importers=1` — PARTIAL: imported only by validation organs (gates, tests, benches): wire it into a shipping program. not adopted: imported only by validation organs (gates, tests, benches): wire it into a shipping program Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, WebAssembly+WASICons behind QEMU (leads); not adopted yet: imported only by validation organs (gates, tests, benches): wire it into a shipping program	●	○	○	◉	○
EMULATE Cortex-M Thumb Measured: `emu_cortexm_run_mem` exists in `runtime/nx_emu_cortexm.nx`, verified at emit. the MCU door: a $5 part is the floor of the sensor-to-supercomputer ladder rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them Adoption: `LIB-GATE-ONLY importers=1` — PARTIAL: imported only by validation organs (gates, tests, benches): wire it into a shipping program. not adopted: imported only by validation organs (gates, tests, benches): wire it into a shipping program Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, WebAssembly+WASICons behind QEMU (leads); not adopted yet: imported only by validation organs (gates, tests, benches): wire it into a shipping program	●	○	○	◉	○
EMULATE LoongArch64 Measured: `emu_loongarch64_run_mem` exists in `runtime/nx_emu_loongarch64.nx`, verified at emit. Chinese sovereign ISA; ours is 6.8 KB and unmeasured rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them Adoption: `LIB-WIRED importers=2 nonval=1` — fully adopted (top of its ladder). Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, QEMU, WebAssembly+WASI; fully adopted on the estate ladderCons none on the measured axes (rival marks are documented presence, not depth)	●	○	◐	◐	○
EMULATE PowerPC64 LE Measured: `emu_ppc64le_run_mem` exists in `runtime/nx_emu_ppc64le.nx`, verified at emit. OpenPOWER, the one big ISA that is actually open rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them Adoption: `LIB-WIRED importers=2 nonval=1` — fully adopted (top of its ladder). Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, WebAssembly+WASI; fully adopted on the estate ladderCons behind QEMU (leads)	●	○	●	◉	○
EMULATE RISC-V RV32 Measured: `emu_riscv32_run_mem` exists in `runtime/nx_emu_riscv32.nx`, verified at emit. the sub-dollar MCU door and the FPGA soft-core door rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them Adoption: `LIB-GATE-ONLY importers=1` — PARTIAL: imported only by validation organs (gates, tests, benches): wire it into a shipping program. not adopted: imported only by validation organs (gates, tests, benches): wire it into a shipping program Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, WebAssembly+WASICons behind QEMU (leads); not adopted yet: imported only by validation organs (gates, tests, benches): wire it into a shipping program	●	○	○	◉	○
EMULATE IBM z/Architecture Measured: `emu_s390x_run_mem` exists in `runtime/nx_emu_s390x.nx`, verified at emit. big-endian mainframe; banking still runs on it rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them Adoption: `LIB-GATE-ONLY importers=1` — PARTIAL: imported only by validation organs (gates, tests, benches): wire it into a shipping program. not adopted: imported only by validation organs (gates, tests, benches): wire it into a shipping program Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, WebAssembly+WASICons behind QEMU (leads); not adopted yet: imported only by validation organs (gates, tests, benches): wire it into a shipping program	●	○	●	◉	○
EMULATE SPARC64 Measured: `emu_sparc64_run_mem` exists in `runtime/nx_emu_sparc64.nx`, verified at emit. delay-slot model shared with mips64 rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them Adoption: `LIB-WIRED importers=2 nonval=1` — fully adopted (top of its ladder). Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, WebAssembly+WASI; fully adopted on the estate ladderCons behind QEMU (leads)	●	○	●	◉	○
UNIFORM DISPATCH ACROSS EVERY EMULATOR Measured: `ic_guest` exists in `runtime/nx_isa_conform_gate.nx`, verified at emit. run_mem is 10 of 10, run is 6 of 10 and load_elf a DIFFERENT 6 of 10 -- measured, so a harness cannot silently test a subset Adoption: `GATE:DEPLOYED-DARK trial=-` — PARTIAL: deployed, no execution surface runs it: admit it to the gate roster. not adopted: deployed, no execution surface runs it: admit it to the gate roster Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, QEMU, WebAssembly+WASICons not adopted yet: deployed, no execution surface runs it: admit it to the gate roster	●	○	○	○	○
ELF LOADER AND CLI FOR THE LIB-ONLY FOUR DARK — `runtime/nx_emu_armv7a.nx` EXISTS but does not declare `emu_armv7a_load_elf`: something shipped at this path under another name, and this mark would read open forever. Repoint the contract to the real entry point (the plan rung AND this row) or rename the function; the flip follows on the next beat, and the `comparewatch-` plane row reads DARK until then. armv7a cortexm riscv32 s390x have run_mem and nothing to feed it from a file rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them watching emu_armv7a_load_elf Pros none measured yetCons behind QEMU (leads); open contract; expected source declaration not established	○	○	○	◉	○
NEW ISA AS A DATA DECLARATION, NOT A HAND-WRITTEN BACKEND DARK — `runtime/_hdl_build/nx_isa_spec.nx` EXISTS but does not declare `isa_spec_target_rows`: something shipped at this path under another name, and this mark would read open forever. Repoint the contract to the real entry point (the plan rung AND this row) or rename the function; the flip follows on the next beat, and the `comparewatch-` plane row reads DARK until then. the axis we intend to win: an LLVM backend or a GCC port is engineer-MONTHS of hand-written target code, a QEMU frontend likewise and it buys execution only [llvmtargets][gccbackends][qemu] watching isa_spec_target_rows Pros none measured yetCons open contract; expected source declaration not established	○	○	○	○	○
ENCODER GENERATED FROM THE SPEC TABLE Measured: `isa_emit` exists in `runtime/_hdl_build/nx_isa_spec.nx`, verified at emit. the incumbent seed: a spec-driven multi-arch encoder whose own header calls itself the capability that removes the last hand-written piece of the code generator Adoption: `LIB-GATE-ONLY importers=2` — PARTIAL: imported only by validation organs (gates, tests, benches): wire it into a shipping program. not adopted: imported only by validation organs (gates, tests, benches): wire it into a shipping program Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, QEMU, WebAssembly+WASICons not adopted yet: imported only by validation organs (gates, tests, benches): wire it into a shipping program	●	○	○	○	○
EMULATOR GENERATED FROM THE SAME TABLE Open — watching `runtime/nx_isa_determinism_gate.nx` : `isa_spec_decoder_gen`, re-measured on every compare beat. Ship that symbol and this mark flips itself; the `comparewatch-` plane row flips with it. in every field stack the assembler and the emulator are written separately and DRIFT; generated from one table they cannot disagree rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them watching isa_spec_decoder_gen Pros none measured yetCons behind QEMU; open contract; expected source declaration not established	○	○	○	●	○
CONFORMANCE KATS GENERATED FROM THE SAME TABLE DARK — `runtime/nx_isa_conform_gate.nx` EXISTS but does not declare `isa_spec_kat_gen`: something shipped at this path under another name, and this mark would read open forever. Repoint the contract to the real entry point (the plan rung AND this row) or rename the function; the flip follows on the next beat, and the `comparewatch-` plane row reads DARK until then. today each KAT block is hand-encoded from a manual, which is why only 2 of 10 arches are measured; generated KATs make the other 8 a declaration watching isa_spec_kat_gen Pros none measured yetCons open contract; expected source declaration not established	○	○	○	○	○
PER-ISA OPPORTUNITY MODEL FROM THE SAME TABLE DARK — `runtime/nx_ribosome.nx` EXISTS but does not declare `isa_opportunity_rows`: something shipped at this path under another name, and this mark would read open forever. Repoint the contract to the real entry point (the plan rung AND this row) or rename the function; the flip follows on the next beat, and the `comparewatch-` plane row reads DARK until then. operator: optimize to each machine's OPPORTUNITIES -- vector width, addressing modes, fused forms, atomics -- read from the declaration rather than hand-tuned per target watching isa_opportunity_rows Pros none measured yetCons open contract; expected source declaration not established	○	○	○	○	○
TIME-TO-NEW-TARGET, MEASURED AND PUBLISHED Open — watching `knowledge/isa_targets.conf` : `isa_newtarget_cost`, re-measured on every compare beat. Ship that symbol and this mark flips itself; the `comparewatch-` plane row flips with it. the done-rule for the whole axis: one NEW ISA from nothing to emit plus emulate plus conformance-green in ONE session, rows-of-data published beside the diff watching isa_newtarget_cost Pros none measured yetCons open contract; expected source declaration not established	○	○	○	○	○
CROSS-ISA BIT-IDENTICAL EXECUTION, AS A REFUSING GATE Open — watching `runtime/nx_isa_determinism_gate.nx` : `rk_isa_determinism`, re-measured on every compare beat. Ship that symbol and this mark flips itself; the `comparewatch-` plane row flips with it. one source, N targets, N sovereign emulators, one required state digest, publish REFUSED on any disagreement -- no field stack gates on this [llvmtargets][gccbackends] watching rk_isa_determinism Pros none measured yetCons open contract; expected source declaration not established	○	○	○	○	○
DIFFERENTIAL ORACLE AS AN ORGAN, NOT A SHELL SCRIPT Open — watching `runtime/nx_isa_oracle_diff.nx` : `iod_run_corpus`, re-measured on every compare beat. Ship that symbol and this mark flips itself; the `comparewatch-` plane row flips with it. supersedes bench/gate_nx_emu_diff.sh which needs WSL, riscv64 binutils and qemu to judge and judges in shell [qemu] watching iod_run_corpus Pros none measured yetCons behind QEMU; open contract; expected source declaration not established	○	○	○	●	○
NX-ISA SPEC AS A TABLE, NOT HAND-WRITTEN CODE Measured: `isa_emit` exists in `runtime/_hdl_build/nx_isa_spec.nx`, verified at emit. a spec-driven multi-arch encoder already exists and is the incumbent every new target must compose Adoption: `LIB-GATE-ONLY importers=2` — PARTIAL: imported only by validation organs (gates, tests, benches): wire it into a shipping program. not adopted: imported only by validation organs (gates, tests, benches): wire it into a shipping program Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, QEMU, WebAssembly+WASICons not adopted yet: imported only by validation organs (gates, tests, benches): wire it into a shipping program	●	○	○	○	○
NXE EXECUTABLE ABI (not ELF, not PE) Source present; authored stronger claim: `nxe_write` in `runtime/nx_nxe_lib.nx`, verified at emit. our own container: no field toolchain defines its own object format and proves it with a conformance gate Adoption: `LIB-WIRED importers=4 nonval=4` — fully adopted (top of its ladder). Pros Source symbol found; stronger capability claim is authored; ahead of LLVM, GCC, QEMU, WebAssembly+WASI; fully adopted on the estate ladderCons none on the measured axes (rival marks are documented presence, not depth)	◉	○	○	○	○
NXE CONFORMANCE GATE, CALLABLE DARK — `runtime/nx_nxeconform_gate.nx` EXISTS but does not declare `nxeconform_registered`: something shipped at this path under another name, and this mark would read open forever. Repoint the contract to the real entry point (the plan rung AND this row) or rename the function; the flip follows on the next beat, and the `comparewatch-` plane row reads DARK until then. PROMOTED-UNREGISTERED measured 2026-09-03: a real 77 KB binary nobody can call watching nxeconform_registered Pros none measured yetCons open contract; expected source declaration not established	○	○	○	○	○
SOVEREIGN VECTOR ISA WITH ITS OWN EMULATOR Source present; authored stronger claim: `sv_run` in `runtime/_hdl_build/nx_simd_isa.nx`, verified at emit. our own vector ISA and simulator in one lib, so a vectorised kernel is provable without vendor silicon Adoption: `LIB-GATE-ONLY importers=1` — PARTIAL: imported only by validation organs (gates, tests, benches): wire it into a shipping program. not adopted: imported only by validation organs (gates, tests, benches): wire it into a shipping program Pros Source symbol found; stronger capability claim is authored; ahead of LLVM, GCC, QEMU, WebAssembly+WASICons not adopted yet: imported only by validation organs (gates, tests, benches): wire it into a shipping program	◉	○	○	○	○
C BACKENDS DECLARED ORACLE-ONLY Open — watching `knowledge/isa_targets.conf` : `isa_oracle_only_decl`, re-measured on every compare beat. Ship that symbol and this mark flips itself; the `comparewatch-` plane row flips with it. the 14 nxc2 C backends need gcc or clang to build, which is a third party in the build path -- operator 2026-09-03 ruled them reference implementations to diff against, re-emitted in NishiLang one target at a time watching isa_oracle_only_decl Pros none measured yetCons open contract; expected source declaration not established	○	○	○	○	○
TARGET DECISION AS DATA, COST MODEL MEASURED Measured: `nx_ribosome_pick` exists in `runtime/nx_ribosome.nx`, verified at emit. the picker is sound but every cost is an NX_MAGIC_<value> constant, i.e. a magic number wearing its own value as a name -- the cost model owes a measurement Adoption: `LIB-WIRED importers=10 nonval=2` — fully adopted (top of its ladder). Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, QEMU, WebAssembly+WASI; fully adopted on the estate ladderCons none on the measured axes (rival marks are documented presence, not depth)	●	○	○	○	○
ORACLE the ISA manuals as ground truth DARK — `knowledge/compare/isa.refs` EXISTS but does not declare `isa_refs_manuals`: something shipped at this path under another name, and this mark would read open forever. Repoint the contract to the real entry point (the plan rung AND this row) or rename the function; the flip follows on the next beat, and the `comparewatch-` plane row reads DARK until then. HONEST STATE: the KAT expectations were encoded from manual knowledge of RISC-V, MIPS64 and the rest, but the MANUALS THEMSELVES ARE NOT MIRRORED -- isa.refs currently pins the four rival pages only. Until each manual is fetched and pinned, the ground truth is unverifiable by a reader, which is exactly the gap this watch names rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them watching isa_refs_manuals Pros none measured yetCons behind LLVM, GCC, QEMU, WebAssembly+WASI; open contract; expected source declaration not established	○	●	●	●	●
ORACLE qemu as differential reference Open — watching `bench/gate_nx_emu_diff.sh` : `iod_qemu_arm`, re-measured on every compare beat. Ship that symbol and this mark flips itself; the `comparewatch-` plane row flips with it. build and test time only, never a runtime or build dependency; the organ that wraps it is the ISA17 contract rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them watching iod_qemu_arm Pros none measured yetCons behind QEMU (leads); open contract; expected source declaration not established	○	○	○	◉	○
ORACLE the RISC-V architectural test suite Measured: `rvc_run_suite` exists in `runtime/nx_rvc_run_suite.nx`, verified at emit. the published conformance suite already has a runner in the estate; it is the model every other ISA's suite should follow rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them Adoption: `REGISTERED-DARK` — PARTIAL: callable, authorised, completed MCP invocation not established by supplied journal window; lifetime history unknown (direct execution may be recorded elsewhere; this scan does not establish lifetime use); no execution surface runs it either (clock, cron, daemon, roster, actlog and surfaced forks checked). not adopted: callable, authorised, completed MCP invocation not established by supplied journal window; lifetime history unknown (direct execution may be recorded elsewhere; this scan does not establish lifetime use); no execution surface runs it either (clock, cron, daemon, roster, actlog and surfaced forks checked) Pros Implementing source symbol found; runtime acceptance separate; ahead of LLVM, GCC, WebAssembly+WASICons not adopted yet: callable, authorised, completed MCP invocation not established by supplied journal window; lifetime history unknown (direct execution may be recorded elsewhere; this scan does not establish lifetime use); no execution surface runs it either (clock, cron, daemon, roster, actlog and surfaced forks checked)	●	○	○	●	○
ORACLE binutils as an assembler cross-check Open — watching `bench/gate_nx_emu_diff.sh` : `iod_asm_crosscheck`, re-measured on every compare beat. Ship that symbol and this mark flips itself; the `comparewatch-` plane row flips with it. riscv64-linux-gnu-as encodes the KAT independently of our hand encoding, which is how an encoding mistake is told from an emulator bug rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them watching iod_asm_crosscheck Pros none measured yetCons behind LLVM, GCC; open contract; expected source declaration not established	○	●	●	○	○
TWIN a published, watchable emulator surface DARK — `runtime/nx_emu_rv64_main.nx` EXISTS but does not declare `isa_emu_page`: something shipped at this path under another name, and this mark would read open forever. Repoint the contract to the real entry point (the plan rung AND this row) or rename the function; the flip follows on the next beat, and the `comparewatch-` plane row reads DARK until then. operator asked for proof that is published and seeable: a served page that runs a KAT on each ISA and shows the trace watching isa_emu_page Pros none measured yetCons open contract; expected source declaration not established	○	○	○	○	○
MINER our ISA target list diffed against the field's Open — watching `runtime/nx_isa_intel.nx` : `ii_targets_diff`, re-measured on every compare beat. Ship that symbol and this mark flips itself; the `comparewatch-` plane row flips with it. GAP-MINING FROM THE ISA UP: diff knowledge/isa_targets.conf (the published denominator this board already cites) against the target lists LLVM GCC and QEMU each publish, emitting ONE headline metric ii_targets_diff = the count of targets they name that we do not. FETCH-PIN-GRADE ONLY: a rival list enters as mirrored bytes plus a number via nx_research_fetch, pinned h<sha256> in isa.refs with an inline citation mark; nothing third-party may enter the build or run path. Becomes an nx_minerhub conf row once it emits JSON, under that hub's admission rule: resolves via sj_allow_path, exits 0, emits the metric as JSON, and reports malformed=0 on its source rival marks uncited — the Yes, Best or Part codes on this row are an observation read with no reference mark behind them watching ii_targets_diff Pros none measured yetCons behind LLVM, GCC, QEMU; open contract; expected source declaration not established	○	●	●	●	○

Rival-claim provenance. Every Yes, Best or Part mark in a rival column is a claim about someone else's product. A cited row carries a reference mark that resolves to a pinned mirror (the refs gate measures that); an uncited row is an observation read and is badged in its evidence until a reference lands. The badge is the receipt, never the proof: a mark proves a mirror exists, not that the mirror supports the code. The rows are counted below.

Rival claims, counted
Class	Count	Note
rows with rival marks	25	rows carrying a Yes, Best or Part in a rival column
cited	1	a reference mark resolves to a pinned mirror
uncited	24	an observation read, badged until a reference lands
rows, summed	25	RECONCILED: the parts sum to the total 25

Delivery and evidence

Inspect risks, technical debt, rendered observations, experiments and references. Read scope and limitations alongside every result.

Release history and work log

The worked plan, on the board. Every leg appends what it measured, landed, retracted, learned and left queued, per rung, so a crash leaves the next seat a ledger here rather than a transcript to mine. Kinds: measure, land, retract, lesson, queue. Newest last.

When	Rung	Kind	Entry
2026-09-03	ISA1	measure	nx_catalog over the ten emulators: all SOURCE-ONLY, 0 built 0 promoted 0 registered 0 invoked. 6 have _main CLIs, 4 are lib-only. Helper names do not collide across all ten, so one gate can import them all.
2026-09-03	ISA1	measure	nx_capsearch over 7250 candidates ranked nx_isa_spec.nx first: a spec-driven multi-arch instruction encoder already exists. It is ABSENT from the laptop tree, so laptop and NAS have forked here.
2026-09-03	ISA1	land	knowledge/isa_targets.conf written, 12059 B verified on disk: the operator's brief plus roughly 40 ISAs it did not name, with impl and ext as separate classes.
2026-09-03	ISA2	land	nx_isa_conform_gate.nx uploaded through the chunked content-put lane, sha 4213cf5c, and BUILT first try at 60976 B with src_sha256 equal to the upload receipt -- the bytes compiled are provably the bytes authored.
2026-09-03	ISA2	measure	first run: rv64 5/6, mips64 4/5, 16 of 17 teeth, verdict RED, ratchet seeded 16 B. nx_organ_ship correctly REFUSED to promote a red gate. Coverage published as a number rather than a verdict, exactly as designed.
2026-09-03	ISA2	retract	the organ's own header claimed neither emulator can return -2. FALSE: nx_emu_rv64.nx defines EMU_RV_RANOFF = -2 and uses it as the initial value of result. Treating it as WRONG-ANSWER would report a structural non-completion as an arithmetic disagreement -- the exact defect this organ refuses, committed inside it. Fixed to a fifth named outcome and the header carries the correction.
2026-09-03	ISA2	lesson	the build was REFUSED by nx_magicratchet for ADDING one inline literal (a 1792 buffer guard). The refusal was right. Fixed by DERIVING the bound from the buffer size and a named longest-row constant rather than renaming the literal. A constant named for its value is still a magic number.
2026-09-03	ISA2	lesson	MCP nx_fs returned "Unable to connect" twice while the estate was healthy. Varying the CLIENT (nxmcp.py over :443) reached the server immediately and revealed the real answer, which was the magic-ratchet refusal. A repeated identical failure is evidence of a shared cause, and the client is shared too.
2026-09-03	ISA5	measure	THE RULER FOUND A REAL DEFECT IN THE SOVEREIGN RV64 INTERPRETER ON ITS FIRST RUN. nx_emu_rv64.nx:163 read: if (w >> 30) & 1 == 0. In this dialect == binds TIGHTER than &, so that parses as (w>>30) & (1==0) = 0, ALWAYS FALSE, and every SRLI silently took the SRAI path. Invisible for non-negative values, which is why the pre-existing positive-only rv64 test never saw it. The 32-bit twin on line 218 has had the parentheses all along: a fix present in one verb and absent from its sibling.
2026-09-03	ISA5	land	Fixed with parentheses, proven by the instrument that found it: rv64 5/6 to 6/6, ratchet TIGHTENED base=5 now=6, the correct polarity for a good-when-higher metric.
2026-09-03	ISA5	measure	Estate-wide census of that precedence shape over buildroot/runtime, corpus_complete=1 across 23520 files: and-1-eq-1 four code sites ALL ACCIDENTALLY CORRECT because 1==1 is 1; and-7-eq-0 two sites both inside COMMENTS; and-0xff-eq zero; and-255-eq ONE site, nx_crypsis_test.nx:29, a REAL defect comparing a single BIT instead of a byte. Two real defects, four fragile-but-correct sites, two comments. Both real ones fixed.
2026-09-03	ISA5	land	MIPS64 conditional branches BEQ BNE BLEZ BGTZ BLTZ BGEZ implemented with the delay slot honoured (target = npc + offset shifted 2, delay-slot instruction always executes). Before this the interpreter could not run a LOOP, so we-emulate-MIPS64 was not a true claim.
2026-09-03	ISA6	land	MIPS64 DSRL made LOGICAL via a new mi_srl mask helper. DSRL and DSRA had been the SAME expression, so one of the two was necessarily wrong.
2026-09-03	ISA7	land	MIPS64 ADDIU made a 32-bit op sign-extended to 64 via a new mi_sx32 helper. ADDIU and DADDIU had shared one code path and were indistinguishable.
2026-09-03	ISA6	lesson	Two edits fired concurrently at the SAME file: one landed, the other was SILENTLY CLOBBERED, and BOTH returned OK. Caught only by grepping for each new form afterwards. Sequential edits from then on.
2026-09-03	ISA5	measure	All three MIPS64 fixes PROVEN by KATs that can actually discriminate: shift-logical-vs-arith needs a DOUBLE shift by 31 because MIPS encodes the shift amount in five bits and one shift by 31 leaves the same low byte under both shifts; addiu-is-32-bit needs the high bits shifted back down because truncation to 32 bits never changes the low byte. coverage rv64 6/6, mips64 7/7, ratchet mips64 4 to 7.
2026-09-03	ISA2	land	nx_isa_conform_gate GREEN 20/20, exit_code 0, NONPASS none. The ruler binds: a regression in either measured ISA fails the gate, and the eight unmeasured arches are named in its own output every run.
2026-09-03	ISA22	land	nx_nxeconform_gate registered and authorised: PROMOTED-UNREGISTERED to REGISTERED. Our own executable format finally has a callable conformance gate.
2026-09-03	ISA2	lesson	A refused build DESTROYED the _build fossil: nx_catalog read BUILT yes 62608 B before an admission refusal and BUILT NO after, while the STAGED artifact survived and promoted cleanly. Any drift instrument comparing against buildroot/_build is silently re-baselined by a refusal.
2026-09-03	ISA9	land	AArch64 KAT block landed and PASSED 4 of 4 on its FIRST measurement: imm-arith, movk-keeps-lanes, madd, cbz-taken, encoded from the Arm ARM. The largest emulator in the set at 18 KB had never been measured at all. Gate 25/25 GREEN, ratchet seeds arm64 at 4, coverage rv64 6/6 mips64 7/7 arm64 4/4, archs_measured 3 of 10.
2026-09-03	ISA26	measure	THE /compare 404 IS AN EDGE OUTAGE, NOT A PUBLISHING BUG, AND THE ORIGIN IS HEALTHY. Measured both sides the same minute: via loopback with correct SNI, sites.elf answers 200 for /compare/isa and 401 for /gallery (alive, auth-gated); via the public edge /compare /gallery /hub /studio ALL answer 404 while / and /video/ answer 200. The 404 body carries the nginx signature, so DSM nginx fronts the sovereign stack and serves a DIFFERENT docroot (the apex links /pages and /posts, absent from sites/nishifamily, and emits X-Nishi-Surface nishipages-apex). The compare gateway was PROVEN innocent: nx_http_probe on loopback 18102 returns 200 for /compare/gpu 106681 B and /compare/isa 89991 B. Filed as debt 1788459203, superseding a July DOES-NOT-REPRODUCE correction and giving open D008 its concrete manifestation. Fix is operator/infra: nginx config lives in the OS namespace the sovereign writer denies by construction.
2026-09-03	ISA26	lesson	I named a cause twice before I had one -- a CMS shadowing the docroot, then a dead supervisor -- and both were retracted from evidence. The second came from reading absence in nx_services as death when nx_services reads a PORTMAP, not the process table. The probe that actually settled it (nx_http_probe, loopback-only) was one cap mint away the whole time. A 404 is the ABSENCE of a diagnosis and it invites the story you already believe.
2026-09-03	ISA5	land	THE PRECEDENCE HAZARD GOT ITS BUS STOP, AND THEN GOT UNWIRED FOR CAUSE. nx_srclint -- the estate lint whose own header says the fifth hand-fix proves the fix belongs in a linter -- was itself BUILT-UNPROMOTED and dark. It is now PROMOTED and REGISTERED (rules 1 and 2 adopted, 19222-file corpus). RULE 3 for the bitwise-vs-comparison trap was written, built and measured: first draft 212 files on the whole corpus, and READING the hits named three false-positive buckets the naive scan could not see -- semicolon-separated statements, a and inside a STRING LITERAL, and separate function arguments. A second draft handling all three STILL reported 212 with a plainly-correct file among them, and the rule does not print its offset so its output cannot be adjudicated without re-deriving every hit by hand. So rule 3 is DELIBERATELY NOT WIRED, with the function, the 212 measurement and the three buckets kept in source as the spec for finishing it. A detector with false positives is worse than none -- that is this organ own standard, and shipping the rule wired would have broken the standard the organ exists to hold.
2026-09-03	ISA26	retract	/compare/isa IS LIVE AND HAS BEEN. Measured from a TRUE EXTERNAL VANTAGE (laptop, curl over the public internet): 200, 89865 bytes, every emulator row rendering; /compare/gpu 200; /gallery 401 auth-gated; / 200. I RETRACT the edge-outage diagnosis I published earlier today and the debt row that carried it (1788459203, now EATEN, superseded by a correction row). THE FALSE MECHANISM: I claimed DSM nginx fronts the estate and 404s every app route. WHY IT LOOKED TRUE: every probe used nx_https_get, which runs ON THE NAS, so it resolves the domain and connects to :443 LOCALLY -- where DSM nginx does listen -- and never traverses the WAN DNAT. THE TRUE PATH: nx_edge_repoint list shows the GL.iNet redirect https-nas wan:443 DNAT to 192.168.8.240:8443 reflection=1, so WAN already reaches sites.elf. A PORT REACHABILITY IS A PROPERTY OF THE VANTAGE, NOT THE HOST -- the estate has that law written down and I did not apply it. A NAS-side HTTP probe cannot measure the WAN path by construction, so every 404 it returned was TRUE about local :443 and IRRELEVANT to the question asked. RECIPE: public surface = curl from the laptop; origin = nx_https_get with the 127.0.0.1:8443 override and correct SNI. Two vantages, two questions, never interchangeable.
2026-09-03	ISA5	land	THE PRECEDENCE BUS STOP IS BUILT, PROVEN AND WIRED, AND THE DEFECT CLASS IS EXTINCT. nx_srclint RULE 3 now runs BY DEFAULT and sits in the name-set ratchet, so any new occurrence fails the lint. Final measurement: 0 hits across 19236 files. Draining it took five passes because the rule reports one hit per FILE: 24 then 14 then 12 then 8 then 5 then 4 then 2 then 0, roughly 70 sites fixed in total. WHAT IT CAUGHT, all real: nx_parallel_run masked a child EXIT STATUS down to bit 0; nx_capability_no_regression_check tested and-2-eq-2, i.e. THE WRONG BIT, inside a regression detector; nx_f32_log_test and nx_f32_activations_test each asserted and-1-neq-1, which is x-and-0 and can NEVER fire -- two vacuous tests; and roughly sixty byte-comparison assertions across the codec, css, layout, palette, tls and crypto suites compared ONE BIT instead of a whole byte, which made those assertions nearly unfalsifiable.
2026-09-03	ISA5	retract	I PUBLISHED A ZERO THAT WAS A FALSE CLEAN AND CAUGHT IT ONLY BY WIRING THE RULE. Mid-drain I measured 0 remaining and said the class was extinct. It was not: the run had been launched as nx_job_run nx_srclint OUT --rule3, and the flag WAS NOT FORWARDED to the organ, so rule 3 never executed and 0 meant DID-NOT-RUN, not CLEAN. Wiring the rule on by default immediately showed 12. A ZERO FROM AN OPT-IN CHECK IS ONLY EVIDENCE IF YOU PROVED THE OPT-IN ARRIVED -- the same shape as a gate that passes because its fixture never reached the condition, and the reason this organ demands a planted positive before believing any clean run.
2026-09-03	ISA5	lesson	A RULE THAT REPORTS ONE HIT PER FILE UNDER-REPORTS A POPULATION AND TURNS A SWEEP INTO A SERIES OF PASSES. Each drain pass revealed the next instance in the same files, which is why the count fell 24-14-12-8-5-4-2-0 instead of going to zero once. The rule is honest but its GRANULARITY is the worklist defect one level down: it should report every site, not the first. Filed as the next improvement to rule 3 rather than left implicit.
2026-09-03	ISA5	land	RULE 3 NOW REPORTS EVERY SITE, NOT ONE PER FILE, AND IS BITE-PROVEN IN BOTH DIRECTIONS. Added sl_next_line and a resume argument so the scan continues past each hit; the caller loops until the rule returns -1. BITE, on the real corpus rather than a fixture: reverting ONE already-fixed line in nx_palette_test.nx to its defective form made the rule fire and name nx_palette_test.nx:74 exactly; restoring the fix made it silent again across 19242 files. Both directions measured, mutation reverted and verified reverted. DECLARED LIMIT, written into the source: the resume is line-granular, so a single line carrying TWO such sites reports only the first -- measured on this tree every offending line carried exactly one, so the floor and the value coincide here, but it is a floor and it is named as one.
2026-09-03	ISA5	lesson	A PLANT THAT THE HARNESS NEVER READ IS NOT A PLANT. The first bite attempt wrote a fixture with three obvious defects to /tmp and ran the lint with --dir at it; the lint answered corpus=1 files, 0 sources and no hits. That reads exactly like a dead rule, and it is not -- the organ never READ the file, so nothing was tested in either direction. The bite that actually proved anything mutated a file already inside the real corpus the organ scans. ASSERT THE FIXTURE WAS REACHED BEFORE READING ITS VERDICT: 0 sources is the tell, and it sits in the same output as the verdict that would otherwise have been believed.
2026-09-03	ISA11	land	RV32 CONDITIONAL BRANCHES IMPLEMENTED, AND RISCV32 MEASURED 6/6 ON ITS FIRST RUN. Reading the decoder showed opcode 0x63 was entirely absent -- the same gap the ruler had named in mips64 hours earlier -- so RV32 could not run a LOOP and "we emulate RV32" was not yet a true claim. Added the full B-type family (beq bne blt bge bltu bgeu) mirroring the RV64 sibling, with the signed forms comparing SIGN-EXTENDED 32-bit values and the unsigned forms comparing the raw masked values, and the 13-bit offset decoded through named constants rather than inline literals. PROVEN by a KAT that could not have passed before it: riscv32.branch-loop got=45 want=45, a sum 0..9 driven by a bne back-branch. Six KATs green: imm-arith, sub, logic, mul, load-store, branch-loop. Gate 32/32 GREEN, ratchet seeds riscv32 at 6, coverage rv64 6/6 mips64 7/7 arm64 4/4 riscv32 6/6, archs_measured 4 of 10.
2026-09-03	ISA11	lesson	RV32I SHARES ITS BASE ENCODING WITH RV64I, SO FIVE OF THE SIX KAT WORD SEQUENCES ARE BYTE-IDENTICAL TO THE RV64 BLOCK. That makes riscv32 the cheapest arch on the board to measure and it is why it was taken next -- but it also means a shared-encoding arch can INHERIT a fixture bug as easily as a fixture. The words reused here are the ones already oracle-verified against riscv64-as and qemu, so the inheritance is of PROVEN bytes, not of assumptions.
2026-09-03	ISA2	land	nx_isa_conform_gate PROMOTED 62616 B and REGISTERED. The first run of the live gate named its own failing KAT: rv64.shift-logical got=255 want=15 WRONG-ANSWER.

On these two registers. Rows are declared in the domain's plan file and carry the debt id, which is the join key back to the sovereign debt plane — that plane, not this page, is the authority on state. Reconciling them automatically (the regen reading the plane and refreshing these rows) is a named, owed rung; until it lands, treat an id here as a pointer to look up, not a status to trust.

Honest verdict. The coverage above records source-symbol presence. Stronger comparisons are authored claims, not measured runtime superiority or accepted outcomes. A watch contract names an expected source symbol; finding it changes source discovery only. Qualification, deployment and runtime acceptance require their own evidence.

Person · product · place — not yet measured for this domain

Every compare carries this layer. Declare knowledge/compare/isa.ppp (rows surface|nishi or c1..c4|label|url|connect naming OUR live surface and each rival's front door), run nx_ppp_probe domain isa, and this section fills itself on the next beat: the same ruler on both sides — privacy and CX (third-party hosts, tracker classes, cookies, security headers), design and longevity (design hygiene, computed WCAG contrast, render-blocking resources, unsized media, script weight, theme and motion queries), findability (landmarks, skip link, on-site search, breadcrumb, headings, internal links).

The field — discovered, not chosen

Rows written by nx_field_discover from isa.seeds: the industry's own lists (Wikipedia wikitext, GitHub topics, awesome lists) read mechanically, every candidate counted across seeds. The matrix columns above are a SEAT'S pick; this band is the population they were picked from, and the stats line measures one against the other. A rival here is a lead, never a verdict — it earns a column when its capabilities are read and pinned.

Discovery receipt. One row per counter the run wrote, in the receipt's own order; the rival rows follow in their own table.

Field discovery, counted
Class	Count	Note
seeds	4
scanned	4
fetched	4
reused	0
failed	0
named	4
candidates	4
mentions	4
capped	0

Rank	Rival	Seeds	Mentions	First seed	Kind	Link
1	LLVM	1	1	col0-llvm	named	https://llvm.org/docs/CodeGenerator.html
2	GCC	1	1	col1-gcc	named	https://gcc.gnu.org/backends.html
3	QEMU	1	1	col2-qemu	named	https://www.qemu.org/docs/master/system/targets.html
4	WebAssembly+WASI	1	1	col3-webassembly	named	https://webassembly.github.io/spec/core/

Exclusive and shared capabilities

One capability is graded on one board; every other board references it. The fleet duplicate census (nx_rivalcensus dupes, on the fleetdupes clock row) reads every board's matrix and names each capability graded as a row on two or more boards, with a home derived from evidence: rung when exactly one board's plan contracts the symbol (that board is starred), gates when no plan contracts it and exactly one board's executed gate map runs the organ's gate (that board is plussed), ambiguous when several boards carry the deciding evidence (a decision for their seats), and none when no evidence decides it, with the reason beside it: unmapped (no board of the duplicate declares a gates map; declare the maps) or unproven (a map exists and runs none of the organ's gates; gate the organ on its proving board, or declare it a shared library by policy). A home elsewhere means this board should carry an @xrow reference to the home board's row rather than a graded row of its own; a home here means the other boards should. The table is this board's slice of one estate-wide census: the shape is shared, the rows are the board's.

This board grades 46 capabilities: 45 exclusive to it and 1 shared with other boards. Shared rows on this page: 1 = home here 0 + home elsewhere 1 + ambiguous 0 + undecided 0 + refused 0 (partition 1); undecided = unmapped 0 + unproven 0 + unevidenced 0; homonyms 0; since the previous census: new 0, resolved 0. Census FRESH age_s=7119.

Capability	Organ	Boards grading it	Home	Rule	Evidence	Standing on this board
rvc_run_suite	`nx_rvc_run_suite.nx`	nishios*, isa	nishios	rung	plan	home elsewhere adopt: `@xrow nishios\|rvc_run_suite\|home by rung (fleet duplicate census)`

Gaps from the record — what the estate does that no board carries

The record census (nx_goalmap record) reads the invoked-tool population and every plan queue row and files each organ or directive that NO matrix, plan or gates row names. A row here is a callout the boards missed: adjudicate it onto a board or declare it infrastructure. Census state STALE (age 1396224 s), sources read 4 of 7 declared — a BLIND census is a FLOOR: unread sources can only add rows.

kind	name	board	source	evidence

rows shown 0|this board's directives 0|estate-wide un-boarded organs 452 (listed in full on /compare/ecosystem)|census rows 639|malformed 0 (counted, never rendered)

References

Beyond a link list. Every reference below resolves twice — the publisher's copy and, where banked, the estate's own non-rottable library mirror with a content pin — and carries its evidence class plus the exact claim on this page it grounds. Keyed marks like [key] in the matrix notes jump here. A dash means honestly absent, never assumed.

[llvmtargets] LLVM Target-Independent Code Generator: the backend architecture and the shipped target list publisher · read in our library knowledge/fetched/cmp_isa_llvmtargets.html · pin hb685725eed84129bbeec780330b72178b69138781db253294ecd01c927988390 · accessed 2026-09-03 · vendor-docGrounds: NEW ISA AS A DATA DECLARATION NOT A HAND-WRITTEN BACKEND
[gccbackends] GCC back ends: the per-target port table and the state of each machine description publisher · read in our library knowledge/fetched/cmp_isa_gccbackends.html · pin h5e4eb84fd52328a99b75d982c7dfca987c429e34da1239336919fd45e8a33fcf · accessed 2026-09-03 · vendor-docGrounds: NEW ISA AS A DATA DECLARATION NOT A HAND-WRITTEN BACKEND
[qemu] QEMU emulated system targets: the machines the reference multi-ISA emulator can execute publisher · read in our library knowledge/fetched/cmp_isa_qemu.html · pin he8f3828b353aa49144a44c1cc8fffc62a1ebeaed238bcd0e97915c136fda5cf8 · accessed 2026-09-03 · vendor-docGrounds: ORACLE qemu as differential reference
[wasmspec] WebAssembly core specification: portability by defining exactly one machine publisher · read in our library knowledge/fetched/cmp_isa_wasmspec.html · pin heb03772fe2e6d42d74ee76387b6689edcb036a669105a4f0526c043c3a91a601 · accessed 2026-09-03 · published-standardGrounds: WebAssembly plus WASI

generated by nx_swcompare_matrix (sovereign NishiLang organ) from knowledge/compare/isa.matrix · source checks show implementation presence; runtime and user-outcome evidence are reported separately · JavaScript supports page controls