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  <id>https://arxiv.org/api/j1WY6tmQuBEw4QoFJyta/ujPLFI</id>
  <title>arXiv Query: search_query=cat:cs.PL AND (all:"effect handlers" OR all:autotuning OR all:"energy-aware" OR all:scheduling)&amp;id_list=&amp;start=0&amp;max_results=12</title>
  <updated>2026-09-22T15:10:25Z</updated>
  <link href="https://arxiv.org/api/query?search_query=cat:cs.PL+AND+(all:%22effect+handlers%22+OR+(all:autotuning+OR+(all:%22energy-aware%22+OR+all:scheduling)))&amp;start=0&amp;max_results=12&amp;id_list=" type="application/atom+xml"/>
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  <entry>
    <id>http://arxiv.org/abs/2609.21284v1</id>
    <title>Authorization Revocation for Long-Running AI Agents: Root-Scoped Quiescence under Delegation and Asynchronous Execution</title>
    <updated>2026-09-18T03:52:46Z</updated>
    <link href="https://arxiv.org/abs/2609.21284v1" rel="alternate" type="text/html"/>
    <link href="https://arxiv.org/pdf/2609.21284v1" rel="related" type="application/pdf" title="pdf"/>
    <summary>Long-running AI agents outlive initiating processes through credentials, delegated tasks, queues, callbacks, reservations, and provider-side operations. Cancellation, process exit, and credential revocation neither close every pre-cut carrier nor distinguish independently authorized shared work. We define root-scoped authorization quiescence: for each manifested sink, a certificate accounts for every cut-relevant acceptance under the retired root-epoch atom that precedes its local fence and excludes protected acceptance under that atom after the fence, while permitting exact rebind to a current, independently sufficient support.
  The root-scoped quiescence protocol linearizes a root cut, fences old-root expansion and protected sinks, represents alternative and conjunctive authority as antichains of minimal sufficient root sets, and composes provider-frontier certificates into a cutset over registered old-root paths. Exact channel-token accounting reconciles transfers; missing or conflicting evidence remains indeterminate. Under stated assumptions, we prove post-cut issuer non-expansion, support-sound projection, compositional soundness under exact channel conservation, independent-support preservation, merge-order independence, and crash/replay stability.
  A provider-free late-effect test suite matches 17/17 registered outcomes. Two cancellation-only and one cut-only execution accept the same class of already scheduled late effect; two cut-plus-fence executions, one restart, and one stale-process execution reject it. A separately implemented checker verifies 17/17 traces and rejects 44/44 consistently rehashed semantic regressions. The certificate establishes root-relative authorization quiescence within its bound manifest and configuration, not global idleness, rollback, or business completion.</summary>
    <category term="cs.PL" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.AI" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.CR" scheme="http://arxiv.org/schemas/atom"/>
    <published>2026-09-18T03:52:46Z</published>
    <arxiv:comment>39 pages, 2 figures, 7 tables; includes a complete proof appendix</arxiv:comment>
    <arxiv:primary_category term="cs.PL"/>
    <author>
      <name>Genliang Zhu</name>
    </author>
    <author>
      <name>Chu Wang</name>
    </author>
  </entry>
  <entry>
    <id>http://arxiv.org/abs/2609.16389v1</id>
    <title>Exo-GPU: Safe, Imperative, User-schedulable Programming for Tensor Cores</title>
    <updated>2026-09-14T21:55:23Z</updated>
    <link href="https://arxiv.org/abs/2609.16389v1" rel="alternate" type="text/html"/>
    <link href="https://arxiv.org/pdf/2609.16389v1" rel="related" type="application/pdf" title="pdf"/>
    <summary>Modern GPUs require not only SIMT-style parallelism but also software-managed concurrency between compute and data movement to reach maximum performance. Performance engineers must reason about subdividing work into the hierarchy of computation resources (threads, warps, warpgroups, blocks, clusters), and, in many cases, also must use asynchronous tensor core and memcpy instructions on different levels of the memory hierarchy (registers, tensor core accumulators, shared memory, global memory). Unlike CPUs, where out-of-order execution is managed by hardware and hidden from programmers, GPUs expose explicit instruction reordering to software through these asynchronous instructions. Well-established GPU programming languages generally offer either direct low-level control without safety guarantees (e.g., CUDA C++ inline assembly or intrinsics) or easier-to-analyze, high-level abstractions (e.g., Triton's tile-based model) that hide asynchronous instructions in the compiler backend, which may prevent performance engineers from maximizing performance by tuning critical details. We propose Exo-GPU, an imperative, low-level language that creates minimal abstraction over CUDA. Our key idea is to treat parallelism and synchronization as mere annotations on sequential code rather than as fundamental control flow primitives, enabling verification that these constructs do not alter the program semantics. The benefit is twofold: programmers can reason about code without hidden control flow or mutation, while allowing the Exo-GPU compiler to verify sequential-parallel equivalence--guaranteeing that parallel execution is functionally equivalent to its sequential interpretation. We used Exo-GPU to author GEMM kernels for the H100 GPU, using wgmma, TMA, and split-k. Our kernels achieved over 80% of theoretical peak on large problem sizes, in some cases outperforming the vendor-provided CUBLAS library.</summary>
    <category term="cs.PL" scheme="http://arxiv.org/schemas/atom"/>
    <published>2026-09-14T21:55:23Z</published>
    <arxiv:comment>29 pages, 22 figures, no conference publication. NOTE: red/blue arcs on page 5 are part of the exposition, NOT editing marks</arxiv:comment>
    <arxiv:primary_category term="cs.PL"/>
    <author>
      <name>David Zhao Akeley</name>
    </author>
    <author>
      <name>Yuka Ikarashi</name>
    </author>
    <author>
      <name>Jonathan Ragan-Kelley</name>
    </author>
  </entry>
  <entry>
    <id>http://arxiv.org/abs/2609.15558v1</id>
    <title>Opportunistic ZGC: Leveraging Idle Cores for More Effective Concurrent Garbage Collection</title>
    <updated>2026-09-14T13:40:04Z</updated>
    <link href="https://arxiv.org/abs/2609.15558v1" rel="alternate" type="text/html"/>
    <link href="https://arxiv.org/pdf/2609.15558v1" rel="related" type="application/pdf" title="pdf"/>
    <summary>Managed language runtimes often provide concurrent garbage collectors so that latency-critical applications with large working sets can keep running while most collection work proceeds in the background. ZGC is a production-quality, generational, concurrent collector in OpenJDK with sub-millisecond pause times. While ZGC is designed to run concurrently, frequent and excessive collections with ZGC can still slow the mutators due to synchronization costs and interference with shared computing resources. Hence, the ZGC scheduler is conservative by default, and in most cases, will grow the heap toward the maximum allowed before scheduling a collection. While this approach minimizes collection effort, it can be wasteful, or even harmful, if the maximum heap size is not well tuned to the actual working set.
  We propose Opportunistic ZGC (OppZGC), a feedback-directed ZGC scheduling policy that constrains the heap dynamically and automatically, without per-application tuning. OppZGC identifies periods when CPU cores are underutilized and leverages them for concurrent collection with ZGC. We describe the design and implementation of OppZGC in OpenJDK's HotSpot Java VM and evaluate it with standard and latency-sensitive benchmarks from DaCapo Chopin and SPECjbb. OppZGC limits heap usage when there is CPU capacity sufficient for additional collections, and avoids scheduling extra collections when they would substantially degrade performance. Overall, it reduces maximum heap usage for our DaCapo benchmarks by between 61% and 90%, on average, depending on configuration, with minimal impact on throughput and request latency compared to default ZGC.</summary>
    <category term="cs.PL" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.DC" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.PF" scheme="http://arxiv.org/schemas/atom"/>
    <published>2026-09-14T13:40:04Z</published>
    <arxiv:primary_category term="cs.PL"/>
    <author>
      <name>Jacob Malloy</name>
    </author>
    <author>
      <name>Michael R. Jantz</name>
    </author>
    <author>
      <name>Terry Jones</name>
    </author>
  </entry>
  <entry>
    <id>http://arxiv.org/abs/2609.11356v1</id>
    <title>Taming Bitwise Behavior in GPU Kernels with Tensor Core: Black-Box Reconstruction, Compiler Enforcement, and Static Verification</title>
    <updated>2026-09-10T10:39:21Z</updated>
    <link href="https://arxiv.org/abs/2609.11356v1" rel="alternate" type="text/html"/>
    <link href="https://arxiv.org/pdf/2609.11356v1" rel="related" type="application/pdf" title="pdf"/>
    <summary>Determinism and numerical reproducibility are increasingly required of GPU kernels in machine learning systems, yet deterministic implementations of the same kernel can still differ bit for bit. Floating-point reduction order is the primary cause, alongside partial-sum precision, fused multiply-add operations, and rounding placement. These choices may be hand-coded, selected by a block-level language such as Triton, or hidden inside a closed-source library such as cuBLAS or rocBLAS. A tile shape chosen for performance therefore also determines the arithmetic, potentially breaking batch invariance. Preserving a fixed order can cost up to 20 percent, while an autotuner cannot identify which configurations are bitwise equivalent.
  We characterize the factors determining the bitwise behavior of reductions and general matrix multiplication (GEMM). First, we introduce a descriptor of GEMM reduction order, including the partitioning of K in split-K GEMM. Using it, we perform the first black-box reconstruction of a closed-source library's arithmetic for bit-level correctness. Our family of Triton GEMMs matches NVIDIA cuBLAS in all tested cases on Blackwell and Hopper. For realistic LLM shapes with fused epilogues, it matches or exceeds torch.compile performance. Second, we enforce balanced-tree reduction during Triton lowering and introduce a data-layout optimization that brings 19 of 27 kernels on GB300 and H100 within 10 percent of free-order performance. Third, we develop sound static checkers for bitwise equivalence between compiled GPU kernels, including the first checker spanning NVIDIA PTX and AMD GCN. Integrated into Triton's autotuner, the checker restricts search to a single bit-equivalence class.</summary>
    <category term="cs.DC" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.PF" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.PL" scheme="http://arxiv.org/schemas/atom"/>
    <published>2026-09-10T10:39:21Z</published>
    <arxiv:primary_category term="cs.DC"/>
    <author>
      <name>Ziteng Yang</name>
    </author>
    <author>
      <name>Nicholas J. Riasanovsky</name>
    </author>
    <author>
      <name>Warren Deng</name>
    </author>
    <author>
      <name>Vivek Sarkar</name>
    </author>
  </entry>
  <entry>
    <id>http://arxiv.org/abs/2609.06443v2</id>
    <title>Expressive power of one-shot control operators and coroutines</title>
    <updated>2026-09-18T10:23:14Z</updated>
    <link href="https://arxiv.org/abs/2609.06443v2" rel="alternate" type="text/html"/>
    <link href="https://arxiv.org/pdf/2609.06443v2" rel="related" type="application/pdf" title="pdf"/>
    <summary>Control operators, such as exceptions and effect handlers, provide a means of representing computational effects in programs abstractly and modularly. While most theoretical studies have focused on multi-shot control operators, one-shot control operators---which restrict the use of captured continuations to at most once---are gaining attention for their balance between expressiveness and efficiency. This study aims to fill the gap. We present a mathematically rigorous comparison of the expressive power among one-shot control operators, including effect handlers, delimited continuations, and even asymmetric coroutines. Following previous studies on multi-shot control operators, we adopt Felleisen's macro-expressiveness as our measure of expressiveness. We verify the folklore that one-shot effect handlers and one-shot delimited-control operators can be macro-expressed by asymmetric coroutines, but not vice versa. We explain why a previous informal argument fails, and how to revise it to make a valid macro-translation.</summary>
    <category term="cs.PL" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.LO" scheme="http://arxiv.org/schemas/atom"/>
    <published>2026-09-06T07:35:08Z</published>
    <arxiv:comment>82 pages, 17 figures. Extended version of a paper presented at APLAS 2025 (LNCS 16201, pp. 88-106, https://doi.org/10.1007/978-981-95-3585-9_5, full version: arXiv:2509.11901)</arxiv:comment>
    <arxiv:primary_category term="cs.PL"/>
    <author>
      <name>Kentaro Kobayashi</name>
    </author>
    <author>
      <name>Yukiyoshi Kameyama</name>
    </author>
  </entry>
  <entry>
    <id>http://arxiv.org/abs/2609.06328v1</id>
    <title>SparseConflicts: Handling Conflicting Data Layouts in Sparse Tensor Contractions</title>
    <updated>2026-09-06T01:25:41Z</updated>
    <link href="https://arxiv.org/abs/2609.06328v1" rel="alternate" type="text/html"/>
    <link href="https://arxiv.org/pdf/2609.06328v1" rel="related" type="application/pdf" title="pdf"/>
    <summary>Optimizing sparse tensor computations is challenging due to the use of compressed storage formats, which leads to non-affine loop nests and a vast, complex schedule space. The performance of a given schedule is sensitive to the sparsity pattern of the input tensors, making it difficult to find a single optimal solution. When input tensors in the same tensor contraction have conflicting data layouts in relation to the iteration order, it requires costly-both in time and memory-layout transformation, such as transposition. A promising but under-explored alternative is to generate a schedule that avoids explicit transposition, but this has not been systematically supported in existing compilers.
  This paper presents a new code generation strategy that generalizes the intermediate representation of the TACO sparse tensor compiler to generate a single loop nest, circumventing explicit transposition of tensors when the tensors have conflicting data layout iteration orders. We extend TACOś iteration graph to express a search-based strategy for locating elements in tensors with conflicting layouts, and we introduce new intermediate representation nodes to lower these schedules to efficient code. This enables the systematic generation of loops that do not require explicit transposition, thus avoiding the overhead of materializing temporary tensors.
  We evaluate our approach on a set of sparse tensor contractions using both real-world and synthetic datasets. Our results demonstrate that for computations with misaligned data layouts, our fused approach achieves up to 2x speedup for some sparsity patterns over the traditional approach of explicitly creating a transposed temporary. We also provide guidelines for when this new scheduling strategy is likely to be beneficial.</summary>
    <category term="cs.PL" scheme="http://arxiv.org/schemas/atom"/>
    <published>2026-09-06T01:25:41Z</published>
    <arxiv:comment>25 pages, 18 figures, 2 tables</arxiv:comment>
    <arxiv:primary_category term="cs.PL"/>
    <author>
      <name>Adhitha Dias</name>
    </author>
    <author>
      <name>Kirshanthan Sundararajah</name>
    </author>
    <author>
      <name>Artem Pelenitsyn</name>
    </author>
    <author>
      <name>Milind Kulkarni</name>
    </author>
  </entry>
  <entry>
    <id>http://arxiv.org/abs/2609.05364v1</id>
    <title>Design Docs Are All You Need: An AI-native Machine-Learning Performance Tool</title>
    <updated>2026-09-04T17:08:51Z</updated>
    <link href="https://arxiv.org/abs/2609.05364v1" rel="alternate" type="text/html"/>
    <link href="https://arxiv.org/pdf/2609.05364v1" rel="related" type="application/pdf" title="pdf"/>
    <summary>Machine-learning performance modeling is a uniquely hostile terrain for long-lived software: the assumptions baked into today's abstractions are invalidated by tomorrow's models and systems, forcing perpetual refactoring of performance-modeling frameworks. Meanwhile, AI coding agents have become fast and capable enough that regenerating an entire library is cheaper than paying down the tech debt of incrementally patching it. We describe SMART, a rigorous symbolic performance-modeling library for ML systems whose main branch contains almost no code: the repository is a DAG of self-contained natural-language design docs, coding sub-agents regenerate the implementation from only the docs on new version updates, and every human change is a natural-language edit to a doc--self-documenting by construction. Two ingredients make regeneration reliable: (i) a design-doc style built around step-by-step worked examples that act as in-context demonstrations for the generating agents, and (ii) a minimal, recursively defined operator IR with symbolic (SymPy) cost expressions, a fast analytical roll-up mode for large sweeps, and a slow modulo-scheduling mode for fine-grained schedule studies. Regenerated implementations reproduce hand-audited reference models--including DeepSeek-V3 serving on a TPU pod slice--to round-off precision, suggesting that design docs--not code--can be the durable artifact for ML-systems co-design tools.</summary>
    <category term="cs.PL" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.AI" scheme="http://arxiv.org/schemas/atom"/>
    <published>2026-09-04T17:08:51Z</published>
    <arxiv:primary_category term="cs.PL"/>
    <author>
      <name>Samuel Kushnir</name>
    </author>
    <author>
      <name>Kimia Noorbakhsh</name>
    </author>
    <author>
      <name>Kavya Sreedhar</name>
    </author>
    <author>
      <name>Liqun Cheng</name>
    </author>
    <author>
      <name>Ming Liu</name>
    </author>
    <author>
      <name>Parthasarathy Ranganathan</name>
    </author>
    <author>
      <name>Mohammad Alizadeh</name>
    </author>
    <author>
      <name>Fred Kjolstad</name>
    </author>
    <author>
      <name>Suvinay Subramanian</name>
    </author>
  </entry>
  <entry>
    <id>http://arxiv.org/abs/2609.03114v1</id>
    <title>Enhancing the Power of Polyhedral-Based Optimizations with Coordinate-Based Hill Climbing</title>
    <updated>2026-09-02T19:50:00Z</updated>
    <link href="https://arxiv.org/abs/2609.03114v1" rel="alternate" type="text/html"/>
    <link href="https://arxiv.org/pdf/2609.03114v1" rel="related" type="application/pdf" title="pdf"/>
    <summary>This paper describes our experience extending the polyhedral compiler Pluto with a lightweight, coordinate-wise hill-climbing tuner that adjusts numeric transformation parameters, such as tile sizes and thread-block dimensions, after Pluto selects the kernel's loop structure. To ensure fast convergence and escape local minima, hill climbing is augmented with two techniques: expanded neighborhood exploration and a shortest-hop refinement phase. On x86 and ARM CPUs, tuned kernels outperform Pluto's default configuration (1.06-1.28x geometric mean speedup across 11 benchmarks) and static optimizers (Clang -O3, Polly, IOOpt), reaching performance competitive with the AutoTVM autotuner at substantially lower search cost. Applying the same technique to GPU thread-block allocation on an NVIDIA A100 yields 5.5-8.5% improvement over default configurations. These results position post-optimization parameter tuning as a practical middle ground between fixed-cost-model polyhedral compilation and full autotuning.</summary>
    <category term="cs.PL" scheme="http://arxiv.org/schemas/atom"/>
    <published>2026-09-02T19:50:00Z</published>
    <arxiv:comment>26 pages, 75 references, 15 figures and 3 tables</arxiv:comment>
    <arxiv:primary_category term="cs.PL"/>
    <author>
      <name>Gaurav Verma</name>
    </author>
    <author>
      <name>Michael Canesche</name>
    </author>
    <author>
      <name>Fernando Magno Quintão Pereira</name>
    </author>
  </entry>
  <entry>
    <id>http://arxiv.org/abs/2609.01771v1</id>
    <title>GadIR: A Spatial-Topology Preserving Compiler for Quantum Many-Body Systems Simulation</title>
    <updated>2026-09-01T18:42:13Z</updated>
    <link href="https://arxiv.org/abs/2609.01771v1" rel="alternate" type="text/html"/>
    <link href="https://arxiv.org/pdf/2609.01771v1" rel="related" type="application/pdf" title="pdf"/>
    <summary>Simulating quantum many-body systems has been one of the most important applications of quantum computation. For simulation, the Hamiltonian of a physical system is compiled into quantum programs with native instructions for quantum hardware. In previous works, the Hamiltonian is represented as Pauli strings, then compiled and optimized based on the quantum circuit model. Such representation paradigm neglects the spatial topology of original physical models, which is vital information to reducing the overhead of compiling many-body systems Hamiltonians.
  To address such neglect, we introduce a spatial-topology preserving compiler for quantum many-body simulation. Using Pauli gadgets as the representations of the Hamiltonian, we introduce our intermediate representation -- GadIR, to preserve the spatial-topology information of original physical models. Our compiler frontend performs the group reduction algorithm based on Pauli gadget model, which is a hardware-independent optimization. Our compiler backend performs trotterization and scheduling on Pauli gadgets, then synthesizes the Pauli gadgets into hardware-native quantum programs. We evaluate our compiler on all the canonical quantum many-body system models, while achieving a significant reduction on compilation overhead regarding four major quantum architectures. Overall, our spatial-topology preserving IR exploits the compilation optimization space for quantum many-body systems Hamiltonian.</summary>
    <category term="quant-ph" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.AR" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.PL" scheme="http://arxiv.org/schemas/atom"/>
    <published>2026-09-01T18:42:13Z</published>
    <arxiv:comment>59th IEEE/ACM International Symposium on Microarchitecture (MICRO 2026)</arxiv:comment>
    <arxiv:primary_category term="quant-ph"/>
    <author>
      <name>Xiangyu Ren</name>
    </author>
    <author>
      <name>Yuexun Huang</name>
    </author>
    <author>
      <name>Zhaohui Yang</name>
    </author>
    <author>
      <name>Yuchen Zhu</name>
    </author>
    <author>
      <name>Tsung-Wei Huang</name>
    </author>
    <author>
      <name>Tsung-Yi Ho</name>
    </author>
    <author>
      <name>Zhiding Liang</name>
    </author>
    <author>
      <name>Antonio Barbalace</name>
    </author>
  </entry>
  <entry>
    <id>http://arxiv.org/abs/2608.14771v1</id>
    <title>From Errors to Proofs: Minimal-Core-Guided Repair for Neuro-Symbolic Constraint Solving</title>
    <updated>2026-08-14T14:48:36Z</updated>
    <link href="https://arxiv.org/abs/2608.14771v1" rel="alternate" type="text/html"/>
    <link href="https://arxiv.org/pdf/2608.14771v1" rel="related" type="application/pdf" title="pdf"/>
    <summary>Making language models solve constraint problems reliably often means having them translate the problem into a formal specification and delegating the search to a sound solver. But the translation is itself a language-model task, and an unfaithful translation makes the solver faithfully solve the wrong problem. Existing pipelines repair only translations that crash, returning the solver's error message and falling silent when the program runs but is wrong. We replace the error message with a proof: when the generated program is unsatisfiable, we extract a minimal unsatisfiable core over the model's own constraints and hand it back the exact set that cannot hold together, a leakage-free signal that localizes the fault. On a new benchmark of 77 problems with an exact oracle, translation to Answer Set Programming is faithful on six of seven domains and fails only on aggregate coverage scheduling, which concentrates the translation tax in one diagnosable pattern. A minimal core, rather than a bare error, is what stops a weaker model from fabricating solutions to infeasible problems, cutting fabrication from 79% to 7%. A strong chain-of-thought baseline meanwhile matches the symbolic route on accuracy, so the route's value is not accuracy but certificates and its refusal to fabricate.</summary>
    <category term="cs.AI" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.CL" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.LG" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.LO" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.PL" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.SC" scheme="http://arxiv.org/schemas/atom"/>
    <category term="math.OC" scheme="http://arxiv.org/schemas/atom"/>
    <published>2026-08-14T14:48:36Z</published>
    <arxiv:comment>7 pages, 2 figures. Accepted at the IJCAI-ECAI 2026 Workshop on Logic and Symbolic Reasoning (LogiSymb), poster</arxiv:comment>
    <arxiv:primary_category term="cs.AI"/>
    <author>
      <name>Dipankar Sarkar</name>
    </author>
  </entry>
  <entry>
    <id>http://arxiv.org/abs/2608.10704v1</id>
    <title>Mixed Choice Multiparty Session Types, Precisely</title>
    <updated>2026-08-11T09:26:24Z</updated>
    <link href="https://arxiv.org/abs/2608.10704v1" rel="alternate" type="text/html"/>
    <link href="https://arxiv.org/pdf/2608.10704v1" rel="related" type="application/pdf" title="pdf"/>
    <summary>A precise (sound and complete) subtyping relation $\leq$ specifies that $T'$ is a subtype of $T$ if and only if a program of type $T'$ can always safely replace a program of type $T$ without compromising the safety of a larger program. This paper formulates and proves preciseness of subtyping for mixed choice multiparty session types with session delegation, creation, and interleaving. We prove soundness by developing the first general type system for a full mixed choice multiparty session $π$-calculus. To prove completeness, we introduce the three-party lock, which is a minimal and general form of liveness error for handling interleaved sessions, and we establish a new proof technique based on a construction of scheduler processes which enable exhaustive detection for all failures of the subtyping relation. We then extend the preciseness results to a family of mixed choice multiparty session types. Algorithms for checking (1) subtyping and (2) safety, deadlock-freedom, and liveness of typing contexts are fully implemented and optimised to run in quadratic time with respect to the size of the state space and typing context, and have been evaluated with (mixed choice) case studies from the literature.</summary>
    <category term="cs.LO" scheme="http://arxiv.org/schemas/atom"/>
    <category term="cs.PL" scheme="http://arxiv.org/schemas/atom"/>
    <published>2026-08-11T09:26:24Z</published>
    <arxiv:comment>107 pages. Full version of paper accepted at ESOP 2027</arxiv:comment>
    <arxiv:primary_category term="cs.LO"/>
    <author>
      <name>Jake Masters</name>
    </author>
    <author>
      <name>Nobuko Yoshida</name>
    </author>
  </entry>
  <entry>
    <id>http://arxiv.org/abs/2608.08765v1</id>
    <title>Bona: Automatic Management of Dirty Ancilla Borrowing in Quantum Circuits</title>
    <updated>2026-08-09T15:28:10Z</updated>
    <link href="https://arxiv.org/abs/2608.08765v1" rel="alternate" type="text/html"/>
    <link href="https://arxiv.org/pdf/2608.08765v1" rel="related" type="application/pdf" title="pdf"/>
    <summary>The management of ancilla qubits has become a critical technique for reducing quantum circuit width. Dirty ancillas, which may be borrowed from any temporarily idle qubit regardless of their initial states, offer substantial flexibility for width optimization, but their use has so far required manual and error-prone handling. We formalize the dirty-qubit borrowing problem and establish a fundamental computational limit by proving its NP-hardness. To support practical optimization, we present \bona, the first scheduler for dirty-qubit borrowing, built on a novel depth-aware heuristic algorithm. We evaluate \bona~ across a variety of benchmarks, including practical quantum circuits and randomly arranged compositions of real circuit modules, and find that it reduces nearly 99\% of dirty ancillas on average with controlled depth overhead. In particular, for parallel quantum walk---an essential component of parallel Hamiltonian simulation---\bona~ matches the circuit width achieved by the clean-qubit schemes of \citeauthor{jiang2024recycling}~(\citeyear{jiang2024recycling}) and \citeauthor{quantinuum}~(\citeyear{quantinuum}), but attains significantly smaller circuit depth, providing concrete evidence that dirty ancillas offer unique optimization advantages in circuits with certain parallelism.</summary>
    <category term="cs.PL" scheme="http://arxiv.org/schemas/atom"/>
    <category term="quant-ph" scheme="http://arxiv.org/schemas/atom"/>
    <published>2026-08-09T15:28:10Z</published>
    <arxiv:primary_category term="cs.PL"/>
    <author>
      <name>Xiaoquan Xu</name>
    </author>
    <author>
      <name>Chenke Liu</name>
    </author>
    <author>
      <name>Boning Meng</name>
    </author>
    <author>
      <name>Zihao Shen</name>
    </author>
    <author>
      <name>Li Zhou</name>
    </author>
  </entry>
</feed>
