Nishi vs the Field -- Sovereign RISC-V Emulator, Bare-Metal Boot and Minimal OS (SOTA)

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Nishi vs the Field

Sovereign RISC-V Emulator, Bare-Metal Boot and Minimal OS — the full field, measured, sourced.

The Nishi sovereign rv64 emulator + never-brick NXE boot loader (nx_boot_run_sov) vs QEMU / Spike / gem5 / Bochs / Unicorn / Firecracker / Renode / coreboot

Capability	Nishi	QEMU	Spike	gem5	Bochs	Unicorn	Firecracker	Renode	coreboot	Notes / source
ISA and execution
RV64I base integer	Yes	Best	Best	Best	No	Yes	No	Yes	No	nx_rv64im_sim + nxc RV64 backend, exhaustively verified on our own emu; QEMU/Spike/gem5 are the ISA bar
RV64M multiply and divide	Yes	Best	Best	Yes	No	Yes	No	Yes	No	full mul/mulh/div/rem with exact RV64 semantics, fuzz-validated; present, not best-in-class
RV64C compressed	Yes	Best	Yes	Yes	No	Yes	No	Yes	No	nx_rvc_expand decodes the C extension
RV64 A / F / D atomic and float	No	Best	Best	Best	No	Part	No	Yes	No	no-float = the measured determinism exceed bet (doctrine); A-atomics = SMP prerequisite, filed F107h; QEMU/Spike/gem5 lead
Privileged M / S / U modes	Part	Best	Best	Best	Yes	No	Part	Yes	Part	Nishi models M-mode CSR + CLINT only (partial); full S/U paging is the QEMU/Spike bar
Multi-ISA guests (x86 / ARM / etc)	No	Best	No	Best	No	Best	No	Yes	No	honest gap: RV64 only; QEMU/gem5/Unicorn are multi-ISA
Performance
Interpreter throughput (MIPS)	~20	~500 (TCG)	~100	~1-5	~50	~100	native	~10	n/a	behavioral step-interpreter measured by nx_emu_bench; QEMU-TCG leads by 1-2 orders
JIT / dynamic binary translation	Yes	Best	No	No	No	Yes	No	No	No	nx_rv64_jit emits real x86-64 (reg-alloc + intra-block control flow + guest memory); QEMU-TCG is the bar
JIT hot-loop throughput (GIPS)	~8	~2-10	n/a	n/a	n/a	~1-5	native	n/a	n/a	measured ~100x over our interpreter on a hot loop; native/QEMU-TCG class
SMP / multicore	No	Best	Yes	Best	Yes	No	Best	Yes	No	honest gap: single-core RV64IM (declared envelope); QEMU/gem5/Firecracker lead
Hardware acceleration (KVM / HVF)	No	Best	No	No	No	No	Best	No	No	honest gap: pure software sim, no host-CPU accel; QEMU-KVM/Firecracker lead
Devices
virtio device models	Yes	Best	Part	Yes	No	No	Yes	Yes	No	rv64im_min_virtio: real split-virtqueue blk/net/rng, drove real entropy end-to-end
UART / CLINT / PLIC	Yes	Best	Yes	Yes	Yes	No	Part	Best	Yes	16550 UART + SiFive CLINT + M-mode timer; Renode/QEMU are the device bar
Full peripheral breadth	Part	Best	Part	Yes	Yes	No	Part	Best	Part	honest partial: a focused device set (UART/virtio/nvme/gpu-model), not QEMU/Renode breadth
Device-tree (FDT) discovery	Yes	Best	Yes	Yes	No	No	Yes	Yes	Yes	nx_hw_discover parses the real QEMU DTB (13 devices at real addresses), no hardcoded list
GDB / debug stub	No	Best	Yes	Best	Yes	Part	No	Best	No	honest gap: no gdbserver/breakpoint stub yet; QEMU/gem5/Renode lead
Snapshot / live migration	No	Best	No	Yes	Yes	No	Best	Part	No	honest gap: no VM snapshot or migration; QEMU/Firecracker lead
Graphical framebuffer / display out	Part	Best	No	Yes	Best	No	No	Yes	Part	rv64im_min_gpu is a command-ring model, no real display output (partial)
Boot and firmware
Bare-metal boot (reset vector to userland)	Best	Best	Yes	Yes	Yes	Part	Yes	Yes	Best	boots POST to mount+replay to verify+execute /sbin/init on OUR silicon model; a genuine strength
Verify-then-execute never-brick loader	Best	No	No	No	No	No	Part	No	Part	EXCEED: NXE SHA-256 integrity gate refuses tampered code BEFORE it executes; no emulator does this
Real-silicon POST / firmware handoff	No	No	No	No	No	No	No	Part	Best	honest gap: guarded never-brick operator step, refused-by-construction in sim; coreboot is the real-firmware bar
UEFI boot support	Part	Best	No	No	Yes	No	No	Part	Yes	nx_boot_uefi models the memmap/handoff in-sim (partial); QEMU/coreboot boot real UEFI
Determinism and sovereignty
Bit-exact determinism	Best	Part	Yes	Yes	Part	Part	No	Part	No	EXCEED: replayable bit-for-bit; validated 0/500 fuzz divergences vs QEMU (integer, no float nondeterminism)
Differential-fuzz validated vs reference	0/500 vs QEMU + 25/25 vs GNU-as	reference	reference	self	self	self	n/a	self	n/a	our stack is validated AGAINST QEMU/GNU-as as oracles; they are the reference, we prove equivalence
Record and replay	Best	Yes	No	Yes	No	No	No	No	No	deterministic replay BY CONSTRUCTION (no rr-style instrumentation needed); QEMU rr-class is opt-in
Own toolchain bits-up (no gcc / llvm)	Best	No	No	No	No	No	No	No	No	EXCEED and alone: nxc to nxasm to RV64, zero external compiler in the whole chain
Zero third-party dependency	Best	No	No	No	No	No	No	No	No	EXCEED and alone: own language, assembler, emulator, TLS, store; competitors lean on gcc/llvm/glibc/host libs
Safety, scale and size
Never-brick by construction	Best	Part	Part	Part	Part	Part	Yes	Part	No	EXCEED: nx_neverbrick_genesis gate RED-flags any unguaranteed firmware-write node; coreboot (real firmware) can brick
Sandbox-contained privileged code	Yes	Yes	Yes	Yes	Yes	Yes	Best	Yes	No	dangerous guest code runs against virtual hardware; a bug crashes the sim, never the host (proven with hostile guests)
Core size (KB)	~189	~50000	~2000	~100000	~10000	~5000	~5000	~50000	~1000	whole sovereign OS+emu core; about 1616x smaller than Puppy Linux

Honest verdict. Nishi is a small, sovereign, behavioral RV64IM emulator that boots bare-metal payloads on its own silicon model (not QEMU) and reaches QEMU-TCG-class throughput on hot loops via its own RV64-to-x86 JIT (~20 MIPS interp to ~8 GIPS JIT, ~100x). It leads, and on several axes is alone: bit-exact determinism (0/500 differential-fuzz divergences vs QEMU, 25/25 encodings byte-identical vs GNU-as), a verify-then-execute never-brick NXE loader (SHA-256 refuse-on-tamper before any code runs), an own toolchain bits-up (nxc to RV64, no gcc/llvm), and zero third-party dependency. Its OS maturity is honestly measured: every software-reachable OS capability is FULL (nx_os_census GREEN 3/3), and the 3 remaining PARTIALs are all hardware-gated (real MMU/CR3, live-GPU BAR, real-silicon POST) and guarded never-brick -- the census refuses to claim the OS is complete. Where it is under SOTA that is filed work, never design (operator law: less-than-SOTA is never design): no A/F/D extensions (A-atomics = the SMP prerequisite -> F107h; no-float itself is the MEASURED determinism exceed bet, not a gap excuse), single-core (SMP -> F107g), no KVM-class hardware accel (after JIT maturity -> F107f), narrower device breadth and no GDB stub / snapshot (-> F107i), and real-silicon POST = the guarded never-brick operator step (-> F002 ULX3S / F103d). Every sub-SOTA axis is a frontier rung with an owner — the climb is the design. RV64 focus is the sovereign mission target (multi-ISA guest emulation is out of mission — stated, not excused). The frontier bets, flagged for research: JIT maturity (MMIO-inside-JIT, cross-block trace chaining, JALR calls), RV64 SMP, and real-silicon POST on 3rd-party metal. Core is ~189 KB (about 1616x smaller than Puppy Linux).

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