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AND PUBLISHED MEASUREMENTS Verified extraction for the Nishi sovereign library, 2026-07-31. Every fact below was read from the primary PDFs. Primary sources: MICRO-54 2021 (M21) https://vortex.cc.gatech.edu/publications/vortex_micro21_final.pdf and arXiv 2110.10857 CARRV 2019 (C19) https://carrv.github.io/2019/papers/carrv2019_paper_10.pdf arXiv 2002.12151 (A20) OpenCL Compatible RISC-V GPGPU CARRV 2022 (C22) https://carrv.github.io/2022/papers/CARRV2022_paper_11_Blaise.pdf ASPLOS 2023 Skybox https://dl.acm.org/doi/10.1145/3582016.3582024 Role in the Nishi ecosystem: EXTERNAL BENCHMARK ORACLE for the sovereign SIMT GPU core (nx_simtcore). No Vortex code, RTL or asset is used. === 1. THE ISA EXTENSION: SIX INSTRUCTIONS === M21 section 1: "by adding only six new instructions to the standard RISC-V ISA, The Vortex processor can execute GPGPU applications and also accelerate the 3D graphics pipeline." M21 section 3.2: "Vortex extends the RISC-V ISA to support GPGPUs by adding six new instructions: wspawn, tmc, split, join, bar, and tex. They are all RISC-V R-Type instructions and fit in one opcode." Table 2 of M21, complete: wspawn %numW, %PC Wavefronts activation tmc %numT Thread mask control split %pred Control flow divergence join Control flow reconvergence bar %barID, %numW Wavefronts barrier tex %dest, %u, %v, %lod Texture sampling and filtering Semantics as stated: wspawn -- activates a number of wavefronts at a specific program PC value, enabling multiple instances of that program to execute independently. tmc -- activates or deactivates threads within a wavefront via a thread mask register, also accessible via the control status registers. split -- pushes the current thread mask state and the branch predication result for all threads onto a hardware immediate post-dominator (IPDOM) stack. join -- pops that entry during reconvergence. bar -- synchronizes wavefront execution; a barrier releases when an expected number of wavefronts reach it. The MSB of the barrier ID indicates GLOBAL (inter-core) rather than local (intra-core) scope. tex -- texture lookup. Uses the R4 format (three source operands u, v, lod). Other texture state (dimension, format, filtering mode, addressing mode, memory address) is configured via CSRs. KNOWN INTERNAL INCONSISTENCY IN M21: section 3.2 says all six are R-Type and fit one opcode, then says tex follows the R4 type format. R-type has two source operands; R4 has three; tex demonstrably needs three. C22 confirms tex is R4. ENCODING: C22 gives the only concrete opcode in the literature -- tex is opcode 0x5B, R4 format, funct3=0, funct2=0, via: .insn r4 0x5b,0,0,%0,%1,%2,%3 C22 section 2.2.2: "The RISC-V specifications reserve four custom opcodes 0x0B, 0x2B, 0x5B, and 0x7B for supporting user-defined extensions." NOT PART OF THE SIX: pred -- explicitly rejected. M21 section 3.1: "In designing the Vortex ISA, we couldn't support predication because of RISC-V dependency." imadd -- a later C22 fixed-point multiply-add extension, R4 format, with the shift constant F encoded in the 2-bit funct2 field as 0->0, 1->8, 2->16, 3->24. clone -- present in C19 only; dropped by A20 and M21. fence -- reused from base RISC-V for memory synchronization; no new instruction. EVOLUTION OF THE COUNT: C19 claims FIVE (wspawn, clone, tmc, split, join). A20 claims FIVE (wspawn, tmc, split, join, bar). M21 claims SIX (adds tex). SKYBOX (ASPLOS 2023) adds a separate graphics set, Table 2: vx_rast %pos, %face, %color, %depth Raster Load vx_rop %a, %b, %c, %shift ROP Store vx_imadd Interpolate and extends vx_tmc to vx_pred. Skybox splits the pipeline: front end (vertex, primitive setup) and fragment shading on the programmable cores; back end (rasterization, interpolation, depth-stencil, blend output) in fixed function. === 2. THREAD MASK AND IPDOM DIVERGENCE -- THE EXACT PROTOCOL === Thread mask semantics, A20: "the thread mask register acts like a predicate for each thread, controlling which threads are active. If the bit in the thread mask for a specific thread is zero, no modifications would be made to that thread's register file and no changes to the cache would be made based on that thread." SPLIT, A20 (the most complete statement; M21 omits the no-divergence case): "If there is only one thread active, or all threads agree on a direction, the split acts like a nop instruction and does not change the state of the warp." When threads DISAGREE, three events occur: 1) The current thread mask is pushed into the IPDOM stack as a FALL-THROUGH entry. 2) The active threads that evaluate the predicate as FALSE are pushed into the stack with PC+4 of the split instruction. 3) The current thread mask is updated to the active threads that evaluate the predicate TRUE. So each divergent split performs TWO pushes. JOIN, A20: pops one entry, giving one of two cases: 1) NOT a fall-through entry: PC is set to the entry's PC and the thread mask to the entry's mask, letting the false-predicate threads follow their own path. 2) IS a fall-through entry: execution continues at PC+4 and the thread mask is restored, which is the case when both paths have been executed. A fully divergent region therefore executes TWO joins. C19 words the push as the INVERSE of the new thread mask, and states that a join without a corresponding split raises an exception. NOTE FOR IMPLEMENTERS: that exception rule conflicts with A20's nop-split rule, because a uniform predicate at run time leaves a correctly balanced join with an empty stack. The Nishi implementation makes join-on-empty a no-op for this reason. The thread mask is readable as a CSR. === 3. WAVEFRONT SCHEDULER === M21 section 4.1.1: the scheduler uses FOUR masks -- 1) an ACTIVE wavefront mask, each bit indicating whether a wavefront is active 2) a STALLED wavefront mask, warps that must not be scheduled temporarily 3) a BARRIER mask, warps stalled waiting at a barrier 4) a VISIBLE wavefront mask, supporting a hierarchical scheduling policy "In each cycle, the scheduler selects one wavefront from the visible wavefront mask and invalidates that wavefront. When a visible wavefront mask is zero, the active mask is refilled by checking which wavefronts are currently active and not stalled." Barrier table entries hold: a counter of wavefronts still required, and a mask of wavefronts stalled by that barrier. === 4. MICROARCHITECTURE === Pipeline: "a standard five-stage in-order RISC-V pipeline". Register file: banked GPRs holding the general-purpose registers for EACH THREAD in EACH WAVEFRONT. M21 Table 1 classifies it as Scalar, 32-bit. M21 never states the register count per thread; C19 states 32. Caches, M21 section 4.1.4: "Each core has an instruction cache and data cache. An optional shared memory is also available that can act as scratchpad memory or a stack depending on the application. Cores can be grouped into a cluster that can optionally be attached to a shared L2 cache. Clusters can share an optional L3 cache. Flush operations among caches are provided as a means of providing weak coherent memory space." Only one cache size is given: 16KB for L1 caches and shared memory. L2 and L3 sizes are not published. High-bandwidth cache: multi-banked, non-blocking, pipelined; each bank has its own MSHR; four stages (schedule, tag access, data access, response) with priority to MSHR replays; a bank selector at the front and a bank merger at the back. Only the DATA cache implements virtual multi-porting -- the instruction cache does not need it because SIMT fetches one instruction per cycle. Maximum 4 virtual ports. Bank count: C19 -- "The number of banks is always kept the same as the number of threads in a warp." Host interface: a command processor (AFU) over PCIe; OPAE driver; CCI-P protocol. Simulation environments: OPAE/ASE, VLSIM (Verilator), RTLSIM, and SIMX (cycle-level). A20 reports SIMX has "a cycle accuracy within 6% of the actual Verilog model." === 5. CONFIGURATIONS === Baseline core: 4 wavefronts x 4 threads (4W-4T). "We picked 4W-4T primarily to allow scaling to 16/32 cores on the target FPGAs while achieving good performance." Configurations evaluated per core: 4W-4T, 2W-8T, 8W-2T, 4W-8T, 8W-4T. Core counts synthesized: 1, 2, 4, 8, 16 on Arria 10; 32 on Stratix 10. Maximum: "Vortex can scale up to 512 total threads on FPGA" (16 threads x 32 cores). Peak performance: 25.6 GFlops at 200 MHz, 32 cores, Altera Stratix 10. Host processor used in evaluation: 3.5 GHz Intel Xeon E5-1650. Cores per cluster: never given as a number. === 6. BENCHMARKS AND MEASUREMENTS -- THE ORACLE === Suite, M21 section 6.1: a subset of the Rodinia OpenCL kernels. COMPUTE-BOUNDED group: sgemm, vecadd, sfilter MEMORY-BOUNDED group: saxpy (printed sxapy, a typo), nearn, gaussian, bfs Only five appear on the figure axes: sgemm, vecadd, sfilter, saxpy, nearn. gaussian and bfs are named in prose only. Texture benchmarks: three synthetic kernels exercising point, bilinear and trilinear filtering, 1080p source into a same-size render target. CRITICAL CAVEAT FOR ANYONE USING THIS AS AN ORACLE: M21 publishes NO per-benchmark absolute IPC in its text. Figures 14 and 19 have y-axes literally labelled CPI while their captions and legends say IPC -- contradictory metrics (reciprocals), and the paper never resolves it. Figures 18 and 21 are raster images with no recoverable text. Any absolute IPC read off those plots is ambiguous by a reciprocal. Absolute IPC is therefore NOT a usable oracle. WHAT IS USABLE -- the quantitative statements M21 makes in prose. All three configs below hold TOTAL THREADS CONSTANT at 16, so they compare how the same threads are PARTITIONED: 4W-4T to 2W-8T (maximize threads): +20 percent speedup on sgemm, +69 percent area in LUT and registers 4W-4T to 8W-2T (maximize wavefronts): -36 percent IPC on sgemm, about -27 percent area Data-cache bank utilization at one port: sgemm 67 percent, vecadd 71 percent; more virtual ports raise this toward 100 percent Cache ports 1 to 2: +9 percent logic area. 1 to 4: +25 percent. "The 2-port configuration has the best balance." Hardware texture unit vs software: bilinear filtering almost 2x speedup on a single core; point sampling negligible Scaling (qualitative only): for compute-bounded benchmarks IPC increases almost linearly with core count; memory-bounded benchmarks still gain, except nearn which is also compute-bound due to a long-latency floating-point square root Table 3, per-core synthesis: config LUT Regs BRAM f(MHz) 4W-4T 21502 32661 131 233 2W-8T 36361 54438 238 224 8W-2T 16981 24343 77 225 4W-8T 37857 57614 247 224 8W-4T 24485 34854 139 228 Table 4, full-system scaling: cores ALM% Regs BRAM% DSP fmax(MHz) FPGA 1 13 78K 10 2 234 Arria 10 2 19 111K 15 5 225 Arria 10 4 30 176K 25 9 223 Arria 10 8 53 305K 45 19 210 Arria 10 16 85 525K 83 38 203 Arria 10 32 70 1057K 23 20 200 Stratix 10 Note the 32-core row is a LARGER device, which is why its percentages fall while core count doubles. The DSP column unit is ambiguous in the PDF; do not cite it as either a percentage or a raw count. Table 5, virtual multi-ported 4-bank data cache: ports LUT Regs BRAM f(MHz) 1 10747 13238 72 253 2 11722 13650 72 250 4 13516 14928 72 244 ASIC: an 8-wavefront 4-thread single core on a 15nm educational cell library, 46.8 mW at 300 MHz, 4KB register file. No absolute area in mm2 is published in any accessible Vortex paper. Area breakdown at eight cores: 53 percent of the Arria 10 logic, dominated by the texture units and caches. The FPU area is low because existing floating-point DSP blocks are used for FMA. SKYBOX ablations: disabling the fixed-function rasterizer changes cycles by about 129 percent on average; disabling fixed-function ROP by about 139 percent; disabling vx_imadd degrades by 33 percent. Skybox configuration: 32 cores as 2 clusters of 16, one rasterizer and one ROP per cluster, 4W x 4T per core, RCACHE 4KB, OCACHE 4KB, TCACHE 8KB per core, ICACHE 16KB per core, block size 4, tile size 32, evaluated on 8 PowerVR SDK demos at Full HD. Skybox reports two conflicting peak fill rates in the same paper: 3.7 GPixels/s in the abstract and section 7.2, versus 29.4 GT/s in the conclusion. Cite deliberately. === 7. GRAPHICS STANCE (M21) === "We opted for a software rendering approach following Larrabee where only texture sampling is accelerated due to limited area on the FPGA... Vortex differs from Larrabee in that only rasterization is offloaded to the FPGA, allowing the geometry processing to execute concurrently on the host processor for load balancing." The graphics API implements OpenGL-ES with geometry processing on the host and the rasterization pipeline running as a kernel on the Vortex cores. Primitives: point, line, triangle. Fragment processing: depth, stencil, fog and alpha tests. Tile rendering follows Larrabee, with tiles generated on the host. Texture unit: point and bilinear sampling on 1D and 2D textures. Trilinear and anisotropic filtering are pseudo-instructions invoking multiple tex operations. Trilinear is literally two tex calls plus a LERP on the fractional lod. The sampler implements ONLY bilinear; point sampling is executed as bilinear with blend values of zero, because the muxing and synchronization needed for a variable-latency sampler is not worth the single cycle saved. Texture unit stages: address generator, texture memory system, texture sampler. The memory unit de-duplicates texel accesses repeated across threads, and the scheduler services one batch fully before starting the next. The sampler performs format conversion and a two-cycle bilinear interpolation, producing one RGBA colour per thread. No FPS, frame counts, or image-quality metrics are published; only execution time in milliseconds for three filter modes across 1, 2, 4 and 8 cores. === 8. CLAIMS FLAGGED AS UNVERIFIED -- DO NOT PROPAGATE === "64 cores / 1024 threads on Stratix 10" is asserted in C22 but its citation resolves to an unrelated reference. No Vortex paper substantiates it. The verified maximum is 32 cores / 512 threads. "6.6x AES-256 speedup" asserted in C22 does not appear in the cited crypto paper, whose own AES figures are 5.0x to 7.0x by mode. arXiv 2505.03102 abstract says up to 4x geomean IPC for hardware warp-level features; its body says 2.42x geomean. Cite 2.42x geomean; 4x is a per-kernel maximum. The Vortex publications page links the OSCAR paper as OpenGPUResearch_OSCAR25.pdf, which returns HTTP 404. The working file is OpenGPUResearch_OSCAR22.pdf. Published FPGA and IPC numbers characterize the 2021 MICRO and 2023 Skybox designs. They do NOT describe the current master branch, which has since renamed ROP to OM and added a windowed fixed-function ISA, a ray tracing unit and a tensor core unit. For reimplementation the repository is normative and the papers are historical. === 9. HOW NISHI USES THIS === The sovereign Nishi SIMT core (nx_simtcore) is written from the first bit in NishiLang on the sovereign RV64IM decoder and ALU. It implements the SIMT capability set benchmarked here -- warps, thread mask, IPDOM split/join divergence, hardware barriers, warp spawn -- under OUR OWN encoding in RISC-V custom-0 (0x0B), deliberately chosen to avoid any collision with the 0x5B that Vortex documents for tex. The capability set is the benchmark; the bits are ours. The gate nx_simtcore_gate tests DIRECTION agreement with the two prose relationships above (2W-8T faster than 4W-4T; 8W-2T slower than 4W-4T on a compute-bound multiply-accumulate kernel at 16 total threads), plus the latency-hiding inversion on a memory-bound kernel. Magnitude parity is explicitly NOT claimed, because our model has no FPU, DRAM controller or FPGA routing. license_tier: ORIGINAL