Source project: Vortex, Georgia Institute of Technology, HPArch lab (PI Hyesoon Kim). Project site: https://vortex.cc.gatech.edu/ Source: https://github.com/vortexgpgpu/vortex Harvested and verified 2026-07-31 for the Nishi sovereign library. Every URL below was fetch-verified. Subject: open-source RISC-V based GPGPU; ISA extension for GPGPU and 3D graphics; FPGA soft GPU; OpenCL/CUDA/Vulkan stack. Why this corpus matters to Nishi: Vortex is the reference open-source GPU architecture used as the external BENCHMARK ORACLE for the sovereign Nishi SIMT GPU core. We take none of their code; we use their published architecture and measurements as a measuring stick. === CORE ARCHITECTURE PAPERS === [VTX-01] Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics Research Blaise Tine, Fares Elsabbagh, Krishna Praveen Yalamarthy, Hyesoon Kim MICRO-54 (54th IEEE/ACM International Symposium on Microarchitecture), 2021 arXiv: https://arxiv.org/abs/2110.10857 PDF: https://vortex.cc.gatech.edu/publications/vortex_micro21_final.pdf DOI: 10.1145/3466752.3480128 THE PRIMARY ISA REFERENCE. Minimal RISC-V ISA extension for GPGPU plus graphics; FPGA soft GPU with OpenCL/OpenGL; scales to 32 cores. NOTE: ACM DL title omits the trailing word Research; the project site and arXiv include it. [VTX-02] Vortex RISC-V GPGPU System: Extending the ISA, Synthesizing the Microarchitecture, and Modeling the Software Stack Fares Elsabbagh, Bahar Asgari, Hyesoon Kim, Sudhakar Yalamanchili CARRV 2019 (Third Workshop on Computer Architecture Research with RISC-V, co-located with ISCA 2019) PDF: https://carrv.github.io/2019/papers/carrv2019_paper_10.pdf Alternate: https://hparch.gatech.edu/papers/elsabbagh_vortex_gpgpu.pdf EARLIEST Vortex paper: the original ISA extension, microarchitecture synthesis, and software stack model. [VTX-03] Vortex: OpenCL Compatible RISC-V GPGPU Fares Elsabbagh, Blaise Tine, Priyadarshini Roshan, Ethan Lyons, Euna Kim, Da Eun Shim, Lingjun Zhu, Sung Kyu Lim, Hyesoon Kim arXiv preprint arXiv:2002.12151, 2020 https://arxiv.org/abs/2002.12151 PDF: https://arxiv.org/pdf/2002.12151 [VTX-04] Implementing Hardware Extensions for Multicore RISC-V GPUs Blaise Tine, Hyesoon Kim CARRV 2022 (6th Workshop on Computer Architecture Research with RISC-V) PDF: https://carrv.github.io/2022/papers/CARRV2022_paper_11_Blaise.pdf Hardware extension mechanism for the multicore Vortex microarchitecture. [VTX-05] A Scalable Multicore RISC-V GPGPU Accelerator for High-End FPGAs Blaise Tine, Fares Elsabbagh, Apurve Chawda, Will Gulian, Yaotian Feng, Da Eun Shim, Priyadarshini Roshan, Ethan Lyons, Lingjun Zhu, Sung Kyu Lim, Seyong Lee, Jeff Vetter, Hyesoon Kim DAC-DIET (Designer/IP/Embedded Track poster), 2021 [VTX-06] Vortex: An Open Source Reconfigurable RISC-V GPGPU Accelerator for Architecture Research Fares Elsabbagh, Blaise Tine, Apurve Chawda, Will Gulian, Yaotian Feng, Da Eun Shim, Priyadarshini Roshan, Ethan Lyons, Lingjun Zhu, Sung Kyu Lim, Hyesoon Kim Hot Chips 32 poster, 2020 PDF: https://vortex.cc.gatech.edu/publications/hotchips-poster.pdf [VTX-07] The Tip of Iceberg in Open-Source Hardware GPU Blaise Tine, Ruobing Han, Hyesoon Kim OSCAR 2022 (Workshop on Open-Source Computer Architecture Research) PDF: https://oscar-workshop.github.io/files/OpenGPUResearch_OSCAR22.pdf DEFECT FOUND IN SOURCE: the Vortex publications page links this as OpenGPUResearch_OSCAR25.pdf, which returns HTTP 404. The OSCAR22 URL above is the working one and matches the project's own news page. === GRAPHICS AND RENDERING === [VTX-08] Skybox: Open-Source Graphic Rendering on Programmable RISC-V GPUs Blaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Paul Cooper, Sam Jijina, Swetha Rajagoplan, Tejaswini Anand Kumar, Jeff Young, Hyesoon Kim ASPLOS 2023 (28th International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3) https://dl.acm.org/doi/10.1145/3582016.3582024 PDF: https://dl.acm.org/doi/pdf/10.1145/3582016.3582024 DOI: 10.1145/3582016.3582024 Talk: https://www.youtube.com/watch?v=yrCnURjnW8w THE PRIMARY GRAPHICS REFERENCE. First open-source full-stack RISC-V GPU supporting Vulkan; hybrid software/hardware graphics rendering microarchitecture. NOTE: author list varies by index (7 vs 11 authors); the 11-author list above matches the ACM record. [VTX-09] Accelerating Graphic Rendering on Programmable RISC-V GPUs (POSTER) Blaise Tine et al. IEEE Hot Chips 34 Symposium, 2022 https://ieeexplore.ieee.org/document/9895607 Precursor poster to Skybox. [VTX-10] Analysis of the RISC-V Vector Extension for Vulkan Graphics Kernels Martin Troiber, Blaise Tine, Martin Schulz, Hyesoon Kim ISPASS 2025 (poster) https://ieeexplore.ieee.org/document/11096397/ Evaluates whether the RISC-V vector extension (RVV) helps Vulkan 3D graphics kernels. === COMPILER AND PROGRAMMING MODEL === [VTX-11] Inside VOLT: Designing an Open-Source GPU Compiler Shinnung Jeong, Chihyo Ahn, Huanzhi Pu, Jisheng Zhao, Hyesoon Kim, Blaise Tine CC 2026 (35th ACM SIGPLAN International Conference on Compiler Construction) https://arxiv.org/abs/2511.13751 DOI: 10.1145/3771775.3786275 Artifact: https://zenodo.org/records/18071633 Repo: https://github.com/vortexgpgpu/Volt Open-source SIMT compiler for Vortex; extends PoCL, CuPBoP and LLVM-RISC-V for CUDA and OpenCL. [VTX-12] SoftCUDA: Running CUDA on Softcore GPU Chihyo Ahn, Ruobing Han, Udit Subramanya, Jisheng Zhao, Hyesoon Kim FCCM 2025, pp. 138-142 https://ieeexplore.ieee.org/document/11008973 DOI: 10.1109/FCCM62733.2025.00049 [VTX-13] Supporting CUDA for an extended RISC-V GPU architecture Ruobing Han, Blaise Tine, Jaewon Lee, Jaewoong Sim, Hyesoon Kim CARRV 2021 PDF: https://carrv.github.io/2021/papers/CARRV2021_paper_66_Han.pdf [VTX-14] Bringing OpenCL to Commodity RISC-V CPUs Blaise Tine, Seyong Lee, Jeff Vetter, Hyesoon Kim CARRV 2021 PDF: https://carrv.github.io/2021/papers/CARRV2021_paper_36_Blaise.pdf [VTX-15] CuPBoP: CUDA for Parallelized and Broad-range Processors Ruobing Han, Jun Chen, Bhanu Garg, Jeffrey Young, Jaewoong Sim, Hyesoon Kim arXiv:2206.07896, 2022 https://arxiv.org/abs/2206.07896 [VTX-16] COX: CUDA on X86 by Exposing Warp-Level Functions to CPUs Ruobing Han, Jaewon Lee, Jaewoong Sim, Hyesoon Kim arXiv:2112.10034, 2021 https://arxiv.org/abs/2112.10034 === WARP-LEVEL FEATURES, ML, CRYPTO, INFRASTRUCTURE === [VTX-17] Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU Huanzhi Pu, Rishabh Ravi, Shinnung Jeong, Udit Subramanya, Euijun Chung, Jisheng Zhao, Chihyo Ahn, Hyesoon Kim DATE 2025, OSSMPIC Workshop (session W05.4.1) https://arxiv.org/abs/2505.03102 DOI: 10.48550/arXiv.2505.03102 DIRECTLY RELEVANT TO SOVEREIGN SIMT DESIGN: adds hardware vx_vote and vx_shfl instructions for warp-level shuffle, vote and cooperative groups. Reports 4x geomean IPC for the hardware implementation over the software one. [VTX-18] Toward End-to-End ML Support on Vortex Shinnung Jeong, Chihyo Ahn, Sai Hemanth Reddy Bheemreddy, Liam Cooper, Krishil Gandhi, Chulhyung Park, Vincent Pham, Huanzhi Pu, Saurabh Singh, Mitul Tandon, Jisheng Zhao, Hyesoon Kim OSCAR 2026 [VTX-19] Cryptography Acceleration in a RISC-V GPGPU Austin Adams, Pulkit Gupta, Blaise Tine, Hyesoon Kim CARRV 2021 PDF: https://carrv.github.io/2021/papers/CARRV2021_paper_87_Adams.pdf [VTX-20] SparseWeaver: Converting Sparse Operations as Dense Operations on GPUs for Graph Workloads Shinnung Jeong, Liam Paul Cooper, Ju Min Lee, Heelim Choi, Nicholas Parnenzini, Chihyo Ahn, Yongwoo Lee, Hanjun Kim, Hyesoon Kim HPCA 2025 https://ieeexplore.ieee.org/document/10946718 [VTX-21] Comparative Analysis of Executing GPU Applications on FPGA: HLS vs. Soft GPU Approaches Chihyo Ahn, Shinnung Jeong, Liam Cooper, Nicholas Parnenzini, Hyesoon Kim IPDPS CGRA4HPC Workshop 2024 https://ieeexplore.ieee.org/document/10596521 [VTX-22] Deploying Vortex FPGA development environment with Apptainer Udit Subramanya, Rahul Raj, Jeff Young, Hyesoon Kim OSCAR 2025 === PROJECT RESOURCES === Workshops and tutorials (MICRO co-located): https://vortex.cc.gatech.edu/micro2025/ MICRO 2025, October 18 2025 https://vortex.cc.gatech.edu/micro2024/ https://vortex.cc.gatech.edu/micro2023/ Open-Source RISC-V Based GPGPU (Vortex) and Their Usage Cases https://vortex.cc.gatech.edu/micro2022/ Open-Source RISC-V Based GPGPU: Vortex and Drone Applications on FPGA https://vortex.cc.gatech.edu/micro2021/ Open-Source RISC-V Based GPGPU Community blog entries: https://vortex.cc.gatech.edu/64b/ 64-bit Extension for Vortex (Rohit Mundada, Hitharth Shajwani, Samarth Agarwal, BITS Pilani) https://vortex.cc.gatech.edu/prefetcher/ Simx Implementation of Cache in Vortex and a HW Prefetcher Design (Vora Mihir Ketan, BITS Pilani) Repositories: https://github.com/vortexgpgpu/ organization https://github.com/vortexgpgpu/vortex main hardware plus software stack https://github.com/vortexgpgpu/vortex_tutorials https://github.com/vortexgpgpu/Volt VOLT compiler Lab and author pages: https://sites.gatech.edu/hparch/publication/ HPArch lab list; a superset of the Vortex site list https://blaisetine.github.io/publications/ Contacts: vortex-dev@lists.gatech.edu, vortexgpu@cc.gatech.edu === PROVENANCE AND RIGHTS === This document is an original Nishi-authored bibliography and commentary. It contains no text copied from the papers themselves. Vortex is used by Nishi strictly as a CAPABILITY BENCHMARK and MEASUREMENT ORACLE. No Vortex source code, RTL, or asset is copied into the Nishi ecosystem. The sovereign Nishi SIMT GPU core is written from the first bit in NishiLang. license_tier: ORIGINAL