026-06-09) Produced by the team's researcher (nx_research_chipfab), NOT a Claude workflow. Corroboration discipline: a fact is ADMITTED only if >=2 independent sources confirm it AND it is cataloged in our verified library. Source corpus = knowledge/library/electronics-fab-deep-research-2026-06-09.txt (the first fab deep-research, 20 confirmed claims, completed before the spend limit). == ADMITTED (spec-buildable; 6 of 8) == [x3] Sovereign silicon floor = the 5-10 MICRON node via DIY photolithography (NOT FDM printing). [x2] Zeloof Z2: 100-transistor NMOS, 10um polysilicon gate, built in a GARAGE (Aug 2021). [x2] CMU Hacker Fab: 952 transistors/chip, 94% yield, improved to 5um (Mar 2026). [x2] Open tool stack: maskless-litho STEPPER from projector parts, RF sputter from ham-radio gear, Arduino-run ALD; open BOMs + SOPs at docs.hackerfab.org; ~7 facilities across 6+ universities. [x3] Fully-printed CPUs are INFEASIBLE -- lithography is the only small-team path to transistors (printed circuits sit orders of magnitude below silicon CMOS; FDM cannot make a doped junction). [x2] Hybrid FHE: print the interconnect/passives/substrate, BUY or self-fab the silicon dies. == OPEN (pursue live via nx_browse_text when egress is up; NAS has egress, sandbox does not) == [pursue] Total sovereign (non-university) replication BOM in dollars. [pursue] Consumable supply chain: wafers, photoresist, dopants, process gases (the real recurring cost). == WHAT THIS MEANS FOR THE ROADMAP (the honest CPU answer) == - "Print a CPU" is a SECOND machine: a maskless-lithography stepper, NOT the FDM print head. FDM ~100,000 nm resolution; a transistor gate is 5,000-10,000 nm (5-10um) at the DIY floor, ~hundreds of nm for modern CPUs. The metrology gate (nx_metrology mt_can_make) enforces this: only SUBMICRON/MICRON class can make a transistor; FDM class makes brackets + PCB traces. - The two machines SHARE the team's substrate: nx_micron_geom (nm coords), nx_motion_plan (a stepper IS an XY motion stage), nx_heater_pid (litho bake/anneal needs precise temp), the geometry/CAD + maturity-auditor + Doctor stack. Building the printer well builds most of the fab. - Realistic target ladder: 4004-class (10um, ~2,300 transistors, Zeloof-proven) -> finer nodes. Modern multi-GHz CPUs at <10nm are NOT a garage target; the honest sovereign goal is a working homemade processor at the micron node, climbing from there. == NEXT (researcher's pursue-list, mechanized) == 1. Live-fetch docs.hackerfab.org BOM + SOPs into the library (rc_live_angle 0) from the NAS. 2. Wafer/resist/dopant supplier survey (rc_live_angle 1) -> the consumable cost model. 3. Maskless stepper repo (github.com/hacker-fab/stepper) -> control-substrate reuse map.