. CAPABILITY RECORD, 2026-07-31. Built from the first bit in NishiLang. Gate nx_simtcore_gate: 23/23 GREEN, exit 0. Source: nishi-silicon/hdl/nx_simtcore.nx + nx_simtcore_gate.nx, mirrored to buildroot/runtime/_hdl_build/. Builds with the sovereign toolchain only: nx_cc -> nxasm_x86, no gcc anywhere in the path. === WHY THIS EXISTS === The ecosystem's OWN ruler named this gap before the work started. nx_sovgpu_census grades the cell "open GPU core on OUR FPGA (Vortex/Nyuzi class)" as GAP, and nx_graphics_board carries real-silicon-gpu-exec as GAP with the sovgpu sub-census at 343 permille. What already existed was NOT this: nx_simt_vec_add and friends are a COMPILER BACKEND emitting PTX/GCN/Metal -- they target somebody else's GPU. rv64im_min_gpu.nx is a command-SUBMISSION model (ring, doorbell, fence) -- the host-to-GPU interface, not an execution engine. Neither is a SIMT core. That was the hole. === WHAT IT IS === A SIMT execution core built on the existing sovereign RV64IM decoder and ALU. Where the scalar core has one PC, one register file and one result per instruction, this has NW warps each with a PC and a THREAD MASK, each warp owning NT threads, and each thread owning its own 32-entry register file. One fetched instruction executes in lockstep across every ACTIVE thread. A masked-off thread commits NOTHING -- no register write, no memory write. That single rule is what makes control-flow divergence expressible on a machine with one program counter. CAPABILITIES, all gate-proven: warps x threads with per-thread register files thread mask control (tmc) IPDOM control-flow divergence (split / join) with the exact published two-push protocol hardware barriers, local and GLOBAL (inter-core) warp spawn (wspawn) warp collectives: shfl, shfl.up, shfl.down, shfl.xor, ballot, all, any, activemask bilinear TEXTURE SAMPLE unit with clamp-to-edge and cross-thread texel de-duplication L1 data cache, 128 sets x 2 ways x 64B = 16KB, LRU, line-granular coalescing channel-arbitrated memory with burst occupancy (bandwidth, not just latency) RAW-hazard register scoreboard (multi-cycle units block their DEPENDENTS, not the warp) MULTI-CORE CLUSTER with SHARED memory channels === ENCODING: OURS, NOT THEIRS === RISC-V reserves four opcodes for user extensions: 0x0B, 0x2B, 0x5B, 0x7B. custom-0 0x0B R-type SIMT control: tmc, wspawn, split, join, bar, tid, wid, ntid custom-1 0x2B R-type warp collectives: shfl / up / down / xor / ballot / all / any / activemask custom-3 0x7B R4-type tex (three sources u,v,lod -- R4 is REQUIRED, R-type cannot carry three) Vortex documents 0x5B for its tex. We deliberately took different opcodes so there is ZERO encoding collision. THE CAPABILITY SET IS THE BENCHMARK; THE BITS ARE OURS. No Vortex code, RTL or asset is copied into the Nishi ecosystem. AND THERE IS NOTHING TO CONFORM TO: as of 2026-07-31 there is NO ratified RISC-V SIMT or divergence extension, and the RISC-V Graphics and Machine Learning SIG repository was ARCHIVED on 2026-04-23. Every credible RISC-V GPU invents its own (Vortex: wspawn/tmc/split/join/bar/tex; Ventus: setrpc/vbranch/join). Custom opcodes are the NORM here, not a shortcut. === MEASURED AGAINST THE VORTEX ORACLE === All oracle numbers were RECOVERED BY RENDERING THE PAPER'S FIGURES at 9x, because they live in chart bitmaps with no PDF text layer -- two separate text-extraction passes reported them as UNKNOWN. See vtx_figure_data_recovered_by_ocr. L1 CACHE, the strongest result. Hardware-vs-software warp reduction: 5.86x WITHOUT a cache, 2.362x WITH it, against Vortex DATE'25's measured 2.42x geomean. Within 2.4 percent. The 5.86x was never a better design -- it was a missing cache. CONFIG RATIOS. Our two memory corners BRACKET Vortex's measured sgemm 2W-8T ratio: 1012 <= 1200 <= 1441 per-mille. The model's parameter space CONTAINS the real device. MULTI-CORE. Aggregate IPC 725 / 1449 / 2986 / 5908 / 11581 per-mille at 1/2/4/8/16 cores, with the efficiency bend appearing at 16 cores -- which is where Figure 18's own bend appears (their sgemm is 100 percent of linear at 8 cores, 89 at 16, 53 at 32). SCOREBOARD. RAW-hazard stalls fall 91 / 16 / 4 as warps rise 2 / 4 / 8, so extra warps demonstrably fill dependency bubbles. === DECLARED LIMITS -- REPORTED, NOT TUNED AWAY === 8W-2T is UNDER-CREDITED: we measure 525..654 per-mille where Vortex measured 735. The cause was identified BY SWEEP, not guessed: execution latency 3/8/16 moves the ratios to 1441/525, 1192/562, 1087/615 -- monotonically toward the target. So the missing mechanism is dependency latency. WE DID NOT ADOPT THE VALUE THAT FITS. No Vortex paper states an FPU latency, and one knob cannot satisfy both targets at once. CHOOSING A CONSTANT BECAUSE IT REPRODUCES THE TARGET IS FITTING, NOT MODELLING. The contention bend is SHALLOW: about 2 percent at 16 cores where the oracle's is 11, because the benchmark kernel is ~98 percent L1-resident so few accesses reach a channel. Mechanism present and non-vacuous; strength under-modelled. Closing it needs a working set larger than L1 -- NOT a smaller channel count, which would be tuning the knob until the curve matched. NO L2 -- deliberately. Their own Figure 21 shows L2 barely moves sgemm (16.5 to 18.5 IPC at 2 channels, NO change at 8) while channels move it 2.4x. BUILD WHAT THE DATA SAYS MATTERS, NOT WHAT THE PAPER LISTS. lod is accepted by tex but selects nothing (single mip level). Declared in-code. Vortex's trilinear is itself a pseudo-instruction issuing two tex ops and lerping on frac(lod). No ray-tracing unit, no tensor cores. Vortex 3.0 (2026-06-09) has both, plus fixed-function raster and Vulkan via a Mesa Gallium driver. The bar moved well past the 2021 paper. === THE NEXT RUNG === Running REAL kernels instead of hand-encoded ones. The recommended path is SPIR-V ingest, NOT PTX: OpenCL SPIR-V subgroup operations (OpGroupNonUniformShuffle, OpGroupNonUniformBallot, OpGroupNonUniformAll/Any) map 1:1 onto the shuffle/vote/ballot already built here, and the LLVM SPIR-V backend is in-tree. PTX is NVIDIA-proprietary and versioned per sm_XX -- a treadmill. See riscv_gpu_and_compiler_stack_sota_2026-07 for the full option ranking and VOLT's measured ~10,400 LoC cost (which assumes a pre-existing LLVM backend). license_tier: ORIGINAL