(2026-06-22) ================================================================== OPERATOR ARC: "for the fpga if there is a way to simulate it lets build that from the hardware rung up on specs, thats the real s class sim type stuff we are working towards." Reframes the doomsday/silicon METAL-01 blocker (a ~$175 ULX3S board) into a buildable, sovereign FPGA-boot SIMULATOR. NEVER-BRICK (#26) is FREE: a simulator writes ZERO real/persistent hardware state — every rung is bounded, total, deterministic, integer-only. SOVEREIGN: every rung is a NishiLang .nx organ compiled by nx_cc -> nxasm_x86 (NO gcc), run by _offc/nx_sov_build_run.elf. Built ON the pre-existing, gated substrate: rv64im_min_sim (behavioral RV64IM CPU that boots a kernel), synth_emit_alu_gates (.nxgate netlist), nx_nxgate_sim (gate-level simulator). THE 9-RUNG LADDER (each GATED — exhaustive-or-broadly-swept, never-brick by construction, liar-killed): R4 nx_fpga_lut.nx / nx_fpga_lut_gate (5/5) — the FPGA ATOM. A LUT4 = 16 SRAM config bits (the per-LUT bitstream) computing ANY 4-input function. Every gate primitive (AND/OR/NOT/XOR/NAND/NOR/XNOR/MUX) tech-maps to exactly one LUT4 bitstream — proven EXHAUSTIVELY (8 primitives x 16 combos = 128 checks, 0 mismatch vs an independent golden model). DFF modeled. R5 nx_fpga_fabric.nx / nx_fpga_fabric_gate (4/4) — a fabric (LUT4 cells + ROUTING) EXECUTES a BITSTREAM. A full-adder (2 cells) + a routed chain (cell wired from another cell's output) run from the bitstream ALONE, exhaustively. The leap: a configured fabric computes real multi-gate circuits knowing only its SRAM. R6 nx_fpga_adder.nx / nx_fpga_adder_gate (5/5) — a WIDE ADD tech-mapped to a LUT4 NETWORK (ripple-carry chain). W=1 & W=4 EXHAUSTIVE, W in {8,16,32} carry-KAT + LFSR == native add (792 checks incl carry-out). R7 nx_fpga_addsub.nx / nx_fpga_addsub_gate (5/5) — an OP-SELECTED ADD/SUB ALU unit. A control bit drives two's-complement (b XOR sub, cin=sub): sub=0 -> a+b, sub=1 -> a-b. Subtraction + op-selection on the fabric. R8 nx_fpga_alu.nx / nx_fpga_alu_gate (4/4) — the LOGIC+ARITHMETIC ALU == the BEHAVIORAL ALU @ 64-bit. A unified datapath (AND/OR/XOR layers + the R7 add/sub + a per-bit result-MUX) runs AND/OR/XOR/ADD/SUB and equals the team's behavioral nx_rv64im_alu_compute at the full RV64 word width: 1050 checks, 0 mismatch. R8b nx_fpga_cmp.nx / nx_fpga_cmp_gate (5/5) — COMPARES SLT/SLTU from the subtractor's INTERNAL signals: SLTU = NOT(carry-out/borrow), SLT = (a_sign XOR b_sign) ? a_sign : (a-b)_sign (overflow-correct). Constant LUTs (all-ones carry-in, all-zero fill). == behavioral, 309 checks each (incl INT_MIN/INT_MAX overflow). R8c nx_fpga_shift.nx / nx_fpga_shift_gate (6/6) — SHIFTS SLL/SRL/SRA as a BARREL SHIFTER (log-depth: 6 MUX stages, stage k shifts by 2^k iff shamt bit k; two control bits unify left/right + arithmetic sign-fill). == behavioral over ALL 64 shift amounts (324 checks/op). => the ENTIRE RV64I base-integer ALU {AND,OR,XOR,ADD,SUB,SLT,SLTU,SLL,SRL,SRA = 10 ops} now runs on the simulated fabric == the behavioral CPU. R9 nx_fpga_decode.nx / nx_fpga_rtype_gate (4/4) — ** an R-TYPE INSTRUCTION DECODES + EXECUTES on the fabric == the behavioral CPU. ** The RV64I R-type DECODER is a fabric ((funct3, funct7 bit5) -> control LUT4s + result class); composed decode-on-fabric -> ALU/shift/compare datapath-on-fabric, vs the behavioral path (decode -> nx_rv64im_alu_compute): 1280 checks across all 10 ops, 0 mismatch; decoder == golden table 16/16. THE CPU's INTEGER EXECUTE STAGE RUNS ON THE SIMULATED FPGA. R10a nx_fpga_seq.nx / nx_fpga_counter_gate (5/5) — the SEQUENTIAL (clocked, stateful) fabric. Adds the DFF + a CLOCK: seq_eval settles combinational logic (DFFs output current Q); seq_tick latches every D->Q simultaneously. A free-running counter (= a PROGRAM COUNTER) holds + increments through a full 2^8 cycle + wraparound. The fabric now has MEMORY + a clock — the foundation for the register file, PC, and a clocked CPU. ECOSYSTEM HOME: nx_fpga_census (GREEN) seeds the 9 cells into the SOVEREIGN seg-store knowledge/store/fpgacen-* (NO TSV; nx_reader_census pattern), byte-verified + GATE-BACKED live (forks the real R9 gate -> 0, neg-control bogus gate -> non-zero). HONEST FRAMING (no overclaim): this is a SIMULATOR. The OmniForge SI (silicon) census cells — place-and-route (nextpnr), bitstream-encoder (prjtrellis), JTAG/loader (OpenOCD), physical FPGA boot (ULX3S ECP5 board) — remain ABSENT on REAL METAL; they need a physical board. This ladder demonstrates the LOGIC path PRESENT-IN-SIM, distinct from physical, and did NOT mutate the OmniForge census (the doomsday SSOT). The R9 execute is composed as decoder-fabric -> datapath-fabric (two chained evals), not yet a single monolithic fabric, and is the R-type integer execute stage — NOT yet a full fetch-decode-execute CPU or kernel boot. LADDER AHEAD: R10 full CPU step (register file + PC via the R10a sequential fabric + instruction fetch + the I/load/store/branch formats, vs rv64im_min_sim) · R9b monolithic single-fabric instruction · R8d MUL/DIV (M-extension) · R-bitstream/place-route serialization · R-board (the one rung that still needs the operator's physical ULX3S — everything up to it is now reproducible in sovereign simulation).