RESEARCH CORPUS (2026-06-20) origin: deep-research run wf_a350a1ae-551 (105 agents, 23 sources, 106 claims, top-25 adversarially verified) + Claude/Nishi-researcher partnership (sovereign fetch nx_omniforge_research_fetch -> knowledge/fetched/of_*.raw) status legend: [VERIFIED n-m] = adversarial vote confirmed; [REFUTED 0-3] = killed; [UNVERIFIED abstain] = sourced but verification could not run (monthly spend limit) -> treat as a LEAD to re-verify, NOT as fact. == TIER: ELECTRONICS / PCB / PASSIVES == [VERIFIED 3-0] LumenPnP v4 open-source pick-and-place throughput = 1580 components/hour (CPH). src: https://www.opulo.io/blogs/news/introducing-lumenpnp-v4 [REFUTED 0-3] LumenPnP v4 places 0402 / 0.4mm-pitch ICs / 0.5mm-pitch BGA. -> DO NOT claim fine-pitch; MEASURE placement accuracy ourselves (corroborates the prior 106-agent finding: LumenPnP placement specs unverified 0-3). [VERIFIED 2-1] Screen-printed R/L/C passives + a full RLC circuit work on flexible plastic; printed inductors+resistors ran a real DC-DC step-up regulator powering OLEDs from a flexible Li-ion battery (printed passives CAN substitute SMD). src: https://www.nature.com/articles/srep15959 (Nature Sci. Reports) [VERIFIED 3-0] Screen-printed carbon-ink (DuPont 7082) resistors: 10 kOhm..1.5 MOhm at 900 Ohm/square sheet resistance, tolerance (std dev) <= 10%. -> this is the achievable home/lab printed-resistor tolerance. src: https://www.nature.com/articles/srep15959 == TIER: SEMICONDUCTOR / GARAGE SILICON == [VERIFIED 2-1] Sam Zeloof Z2 = 100 transistors (10x10 array), 10 micron polysilicon-gate process (same generation as Intel's first CPU), fabricated in a garage with NO cleanroom + impure chemicals; ~1,500 transistors across 15 chips. src: https://sam.zeloof.xyz/second-ic/ [VERIFIED 3-0] Z2 vs Z1: Z1=6 transistors, aluminum gate, Vth>10V (needed 9V batteries). Z2 self-aligned polysilicon gate: Vth=1.1V, on/off ratio 4.3e6, leakage 932 pA (Vds=2.5V), compatible with 2.5V/3.3V logic. src: https://sam.zeloof.xyz/second-ic/ [UNVERIFIED abstain] Zeloof BUYS wafers pre-deposited with gate oxide (~10nm SiO2) + polysilicon (300nm) to avoid toxic silane; sourced 25x 200mm wafers on eBay for $45 -> key feedstock effectively "must be bought". (1-0, re-verify) [UNVERIFIED abstain] Hacker Fab BOM (build/buy, USD): litho stepper ~$3,015; vacuum spin coater $200; tube furnace $200; thermal evaporator $15,000; plasma etcher $17,400 (buy); probe station $15,800 (buy). src: hackerfab.org (re-verify) [UNVERIFIED abstain] Open-source maskless DLP-projector stepper buildable ~$3,000, optical resolution <2 micron; claims NMOS capability (no measured yield/count on the abstract). src: https://arxiv.org/abs/2510.15082 (re-verify) -> Gershenfeld doctrine (prior research): "chips and stepper motors stay bought" = the irreducible buy-line. == TIER: NO-FLOAT / SURVIVAL COMPUTING == (all UNVERIFIED abstain — spend limit; primary sources, high prior, re-verify) [UNVERIFIED] Collapse OS: built in Forth; targets Z80/8086/6809/6502; core (ex machine ports) < 2000 LOC, builds with cc+make. src: https://collapseos.org/ , https://collapseos.org/forth.html [UNVERIFIED] Dusk OS: 32-bit Forth, "big brother" to Collapse OS; targets i386/amd64/ARM/RISC-V/m68k (~30yr-old machines); bare-metal i386 (FAT16 + C compiler + i386 asm + Grid editor) < 6000 LOC total; self-hosts on all targets. src: https://duskos.org/ , https://git.sr.ht/~vdupras/duskos -> design lesson for our NF leg: Forth-class minimal bootstrap + self-hosting is the proven survival-compute pattern. == TIER: MECHANICAL BOOTSTRAP (tools that make tools) == (UNVERIFIED abstain — re-verify) [UNVERIFIED] Gingery 7-book dependency chain: (1) Charcoal Foundry -> (2) Metal Lathe -> (3) Metal Shaper -> (4) Milling Machine -> (5) Drill Press -> (6) Dividing Head -> (7) Sheet Metal Brake. src: en.wikipedia.org/wiki/David_J._Gingery Flat-reference generation = Whitworth three-plate method (bootstraps a flat datum from nothing). RepRap principle: a 3D printer prints a large fraction of its own structural parts; "vitamins" (motors, rods, electronics, hotend) cannot be printed -> the self-replication loop is PARTIAL, not closed. KEY SOURCE LIST (for citation / >=2-source corroboration; quality tags): primary: opulo.io (LumenPnP v4), nature.com/articles/srep15959, sam.zeloof.xyz/second-ic, hackerfab.org, arxiv.org/abs/2510.15082, collapseos.org(+/forth.html), duskos.org, git.sr.ht/~vdupras/duskos secondary: en.wikipedia.org/wiki/{David_J._Gingery,RepRap,Open_Source_Ecology}, swellai Gershenfeld transcript, hackaday home PCB etching, bigmessowires hot-plate reflow reference: ericweinhoffer Whitworth three-plates, handwiki Surface_plate, learn.cemetech.net Z80 math routines OMNIFORGE IMPLICATION (how this shapes our build order): * The DESIGN+OUTPUT software legs (CAD kernel, slicer/G-code, PCB/EDA -> Gerber, HDL) are FULLY sovereign-buildable, integer-only, and are where we already lead -> build these deep first. * The PHYSICAL floor has a hard buy-line: silicon wafers/feedstock, stepper motors, certain chemicals/optics ("stay bought"). Honest doomsday plan = own ALL the design/automation/control software + the machines that can be made from printed/milled parts; depend on a SMALL, explicit external feedstock set (the MS supply-bottleneck map). * Printed passives (R: <=10% tol, L, C) ARE home-fabricable -> a real near-term EXCEED lane for the ED leg. * Garage silicon floor is ~10 micron / ~100s of transistors (Zeloof) — enough for a minimal no-float core in principle, but the realistic sovereign chip path is FPGA-hosted soft-core (nishi-silicon RV64IM-min) first, garage-litho aspirational.