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The CAKEs and the IFOP(Infinity Fabric On Package) IP will be on both the Zen-2 Die/Chiplet side and the I/O Central Die side so that there can be Infinity Fabric traffic between the respective Zen-2 Die/Chiplet and the Central I/O die
from the top result below
https://pcper.com/2018/11/amd-shows-off-zen-2-based-epyc-rome-server-processor/
This new approach allows each chip to directly access up to eight channels of DDR4 memory (up to 4TB) and will no longer have to send requests to neighboring dies connected to memory which was the case with, for example, Threadripper 2
https://pcper.com/2013/07/nvidia-shield-review-tegra-4-android-gaming-and-pc-game-streaming/
If you have to, a micro-USB to Ethernet adapter can be used when performance is critical