nx_simd_isa.nx

nx_simd_isa.nx -- a sovereign VECTOR ISA + SIMD emulator, so vectorized kernels run as real vector MACHINE CODE and are proven by EXECUTION (the way we proved the scalar RV64/ARM/x86 emit). Bits-up: Nishi has its own vector extension; the AVX2 / NEON / RVV emit is then a DEPLOY-TIME lowering of this ISA to whatever vector unit the spore/seed lands on (vertical co-design at the deploy boundary). 8 vector registers x SV_W lanes (i64). Instruction = 2 words: [op|vd|va|vb, imm]. Ops: VLOAD vd,[imm] VSTORE [imm],va VADD/VMUL/VSUB vd,va,vb. One vector op does SV_W lanes -- the throughput the uops.info/nanoBench cost model prices.