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nxasm_arm64_enc.nx

buildroot/runtime/nxasm_arm64_enc.nx

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about

DEFINITION-COMPLETE: one function per A64 instruction. Encoders with no caller yet are the backend still being built, NOT dead code -- deleting them would strip the capability under construction. Declared so the reachability census buckets them instead of ratcheting them as debt. nxasm_arm64_enc.nx -- sovereign aarch64 (A64) instruction encoder + ELF writer, written in NishiLang. The aarch64 sibling of nxasm_x86_enc.nx (x86_64) and asm_enc.nx (RV64). All A64 instructions are fixed 32-bit, emitted little-endian. Pure bit-manipulation -- no syscalls in the encode functions (arch-neutral, KAT-able under any lane). Each encoder returns the 32-bit word; the ELF writer + a64_put_u32le handle emission. Validated byte-exact vs the ARM A64 ISA (Arm ARM DDI 0487) -- the spec is the oracle (per the externals-as-oracle cardinal); golden words are cross-checked against canonical forms (mov x0,x1=0xAA0103E0, mul x2,x0,x1=0x9B017C02, sdiv x0,x1,x2=0x9AC20C20, ldr x0,[x1,#8]=0xF9400420). genealogy_id: arm_a64_isa_ddi0487 + osdev_elf lineage_id: nishi_sovereign_aarch64_encoder_m6 license_tier: ORIGINAL

dependencies 0 imports · 1 importers

nxasm_arm64_enc.nx nx_arm64_e2e_test.nx

imports: none

imported by: nx_arm64_e2e_test.nx

structs

none

consts

22const A64_XZR: i64 = 31
23const EM_AARCH64: i64 = 183 // 0xB7
24const A64_BASE: i64 = 0x10000
25const A64_HDRLEN: i64 = 120 // 64 ehdr + 56 one phdr

functions

28func a64_put_u32le(out: *u8, o: i64, w: i64) -> i64
35func a64_put_u64le(out: *u8, o: i64, v: i64) -> i64
42func a64_enc_movz(sf: i64, Rd: i64, imm16: i64, hw: i64) -> i64
45func a64_enc_movn(sf: i64, Rd: i64, imm16: i64, hw: i64) -> i64
48func a64_enc_movk(sf: i64, Rd: i64, imm16: i64, hw: i64) -> i64
54func a64_mov_imm64(out: *u8, o: i64, Rd: i64, imm: i64) -> i64
66func a64_enc_add_imm(sf: i64, Rd: i64, Rn: i64, imm12: i64, sh: i64) -> i64
69func a64_enc_sub_imm(sf: i64, Rd: i64, Rn: i64, imm12: i64, sh: i64) -> i64
72func a64_enc_subs_imm(sf: i64, Rd: i64, Rn: i64, imm12: i64, sh: i64) -> i64
75func a64_enc_cmp_imm(sf: i64, Rn: i64, imm12: i64) -> i64
80func a64_enc_add_shifted(sf: i64, Rd: i64, Rn: i64, Rm: i64, shift: i64, imm6: i64) -> i64
83func a64_enc_sub_shifted(sf: i64, Rd: i64, Rn: i64, Rm: i64, shift: i64, imm6: i64) -> i64
86func a64_enc_subs_shifted(sf: i64, Rd: i64, Rn: i64, Rm: i64) -> i64
89func a64_enc_cmp_reg(sf: i64, Rn: i64, Rm: i64) -> i64
94func a64_enc_orr_shifted(sf: i64, Rd: i64, Rn: i64, Rm: i64, shift: i64, imm6: i64) -> i64
97func a64_enc_and_shifted(sf: i64, Rd: i64, Rn: i64, Rm: i64) -> i64
100func a64_enc_eor_shifted(sf: i64, Rd: i64, Rn: i64, Rm: i64) -> i64
103func a64_enc_mov_reg(sf: i64, Rd: i64, Rm: i64) -> i64
108func a64_enc_madd(sf: i64, Rd: i64, Rn: i64, Rm: i64, Ra: i64) -> i64
111func a64_enc_mul(sf: i64, Rd: i64, Rn: i64, Rm: i64) -> i64
115func a64_enc_div(sf: i64, Rd: i64, Rn: i64, Rm: i64, is_signed: i64) -> i64
122func a64_enc_csinc(sf: i64, Rd: i64, Rn: i64, Rm: i64, cond: i64) -> i64
125func a64_enc_cset(sf: i64, Rd: i64, cond: i64) -> i64
132func a64_enc_shiftv(sf: i64, Rd: i64, Rn: i64, Rm: i64, op2: i64) -> i64
140func a64_enc_ldst_reg(size: i64, L: i64, Rt: i64, Rn: i64, Rm: i64) -> i64
145func a64_enc_ldr_uimm(size: i64, Rt: i64, Rn: i64, imm12: i64) -> i64
148func a64_enc_str_uimm(size: i64, Rt: i64, Rn: i64, imm12: i64) -> i64
156func a64_enc_sturldur(L: i64, Rt: i64, Rn: i64, imm: i64) -> i64
159func a64_enc_stur(Rt: i64, Rn: i64, imm: i64) -> i64 { return a64_enc_sturldur(0, Rt, Rn, imm) }
160func a64_enc_ldur(Rt: i64, Rn: i64, imm: i64) -> i64 { return a64_enc_sturldur(1, Rt, Rn, imm) }
166func a64_enc_ldstp(idx: i64, L: i64, Rt: i64, Rt2: i64, Rn: i64, imm: i64) -> i64
170func a64_enc_stp_pre(Rt: i64, Rt2: i64, Rn: i64, imm: i64) -> i64 { return a64_enc_ldstp(3, 0, Rt, Rt2, Rn, imm) }
171func a64_enc_ldp_post(Rt: i64, Rt2: i64, Rn: i64, imm: i64) -> i64 { return a64_enc_ldstp(1, 1, Rt, Rt2, Rn, imm) }
172func a64_enc_stp_off(Rt: i64, Rt2: i64, Rn: i64, imm: i64) -> i64 { return a64_enc_ldstp(2, 0, Rt, Rt2, Rn, imm) }
173func a64_enc_ldp_off(Rt: i64, Rt2: i64, Rn: i64, imm: i64) -> i64 { return a64_enc_ldstp(2, 1, Rt, Rt2, Rn, imm) }
176func a64_enc_b(off: i64) -> i64
179func a64_enc_bl(off: i64) -> i64
182func a64_enc_bcond(cond: i64, off: i64) -> i64
185func a64_enc_cbz(sf: i64, Rt: i64, off: i64) -> i64
188func a64_enc_cbnz(sf: i64, Rt: i64, off: i64) -> i64
191func a64_enc_ret() -> i64 { return 0xD65F03C0 }
192func a64_enc_br(Rn: i64) -> i64 { return 0xD61F0000 | ((Rn & 0x1F) << 5) }
193func a64_enc_blr(Rn: i64) -> i64 { return 0xD63F0000 | ((Rn & 0x1F) << 5) }
194func a64_enc_svc0() -> i64 { return 0xD4000001 }
199func a64_build_elf(code: *u8, code_len: i64, out: *u8) -> i64