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rvv_regname_test.nx

buildroot/runtime/rvv_regname_test.nx

3928 B107 linesdepth 6pulls 14 transitivereach 0 importersview sourcekind gate/proof
docsdependenciesstructsconstsfunctions

about

rvv_regname_test.nx -- reg_name + vbinop lowering dispatch. Exercises the RVV branch added to reg_name() AND the vadd.vv / vfadd.vv emission from rv_emit_vbinop. Full vector codegen lands when the IR + allocator are wired end-to-end; for now this confirms the naming + mnemonic surface is correct.

dependencies 6 imports · 0 importers

syscalls.nx types.nx ir.nx outbuf.nx regalloc.nx riscv.nx rvv_regname_test.nx

imports: syscalls.nxtypes.nxir.nxoutbuf.nxregalloc.nxriscv.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main out_new sys_mmap reg_name out_str out_char out_i64 out_char ↻ sys_mmap ↻ is_vec_reg emit_vbinop_mnem out_str ↻ buf_contains ir_function_new sys_mmap ↻ ir_type_i64 alloc_type sys_mmap ↻ ir_block_new nx_assert_ptr sys_write nx_puts_err sys_write ↻ nx_assert sys_write ↻ nx_puts_err ↻ nx_assert_lt sys_write ↻ nx_puti_err sys_mmap ↻ sys_write ↻ nx_puts_err ↻ alloc_value nx_assert_ptr ↻ nx_assert ↻ nx_assert_lt ↻ ir_emit_binop nx_assert_ptr ↻ nx_assert ↻ alloc_instr

structs

none

consts

none

functions

15func buf_contains(buf: *u8, n: i64, needle: *u8) -> i64 {
called by 1: main
33func main() -> i64 {
calls 12: out_newreg_nameis_vec_regemit_vbinop_mnembuf_containsir_function_new+6