simd.nx

simd.nx -- SIMD vector types + intrinsics (spec + soft-fallback). Target: 8-16x speedup on every numeric routine NishiLang ships (sha256, chacha20, base64, CRCs, etc.) via target-native vector instructions (AVX-512, RVV, NEON). Two-phase approach: Phase A (this file): define the SIMD type API + soft-fallback implementation. Every SIMD op is a regular i64 function that manipulates an "8x i64" packed buffer one lane at a time. No speedup yet, but callers can write SIMD-shaped code today. Phase B (riscv.nx backend work, pending): pattern-match these functions during codegen and replace with single vector instructions. Same source code compiles to 8-16x faster machine code. Why this order: API commitment FIRST means library authors can start writing SIMD-shaped routines now. The speedup lands later without breaking any caller. Invariants: V1 Vec64 is 8x i64 = 64 bytes = one AVX-512 register / two AVX2 regs / one RVV VLEN-512 register / four NEON regs. V2 Ops are pure functions of operand lanes -- no side effects, no aliasing concerns. V3 Memory ops (load/store) take aligned pointers; caller ensures 64-byte alignment for max throughput.