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sketch_observability_dashboard_bench.nx

buildroot/runtime/sketch_observability_dashboard_bench.nx

6663 B192 linesdepth 6pulls 14 transitivereach 0 importersview sourcekind benchtopic sketch
docsdependenciesstructsconstsfunctions

about

sketch_observability_dashboard_bench.nx -- COMPOSITION integration bench. CLAIM TO VALIDATE: Substrate composes -- multiple sketches running on the SAME stream stay sub-linear in memory AND each track its metric accurately. This integration bench demonstrates the cardinal "composition over configuration": a realistic observability workload built from 4 sketches running side-by-side. WORKLOAD (simulated APM telemetry): For each of 5000 events: event.user_id -> HLL (track unique users) event.event_id -> CountSketch (estimate per-event frequencies, spotting top events) event.latency -> T-Digest (latency percentiles) event.latency -> AMS (F_2 = skew indicator) - user_ids range over 200 distinct (skewed to first 50) - event_ids range over 20 distinct (heavy tail at id=1) - latencies log-uniform in [1, 10000] microseconds MEMORY BUDGET: HLL lg_k=8: 256 + 32 = 288 B CountSketch d=5 w=256: 10288 B (counter grid 10240 + header) T-Digest delta=100: ~20 KB AMS d=5 s=128: 5120 + 80 = 5200 B TOTAL: ~36 KB. vs naive (5000 event records × ~40 B): 200 KB. SUB-LINEAR composition wins on memory. EACH METRIC VERIFIED INDEPENDENTLY: - HLL within 25% of 200 unique users - CountSketch correctly identifies event_id=1 as heaviest - T-Digest p99 within 30% of true p99 latency - AMS F_2 within 50% of true F_2 (skew indicator)

dependencies 6 imports · 0 importers

syscalls.nx sketch_hll.nx sketch_count_sketch.nx sketch_tdigest.nx sketch_ams.nx sketch_types.nx sketch_observability_dashboard

imports: syscalls.nxsketch_hll.nxsketch_count_sketch.nxsketch_tdigest.nxsketch_ams.nxsketch_types.nx

imported by: nobody (leaf or entry point)

call flow from main pre-order; caps 40 nodes / depth 6 declared; ↻ = already shown

main nx_hll_alloc nx_cs_alloc nx_tdigest_alloc nx_ams_alloc write_bod nx_hll_add murmur3_32 mm_load_u32_le mm_rotl32 nx_clz32 nx_bits_clz32 nx_cs_add nx_cs_h1 nx_cs_h2 nx_cs_sign nx_ams_add nx_tdigest_add nx_tdigest_merge nx_tdigest_sort_buffer nx_tdigest_centroid_at nx_tdigest_w_max nx_hll_estimate nx_hll_pow2_neg_q32 nx_hll_alpha_m_sq_q64 nx_hll_bias_table_n nx_hll_bias_table_get nx_hll_bias_lgk4 nx_hll_bias_lgk5 nx_hll_bias_lgk6 nx_hll_bias_lgk7 nx_hll_bias_lgk8 nx_hll_bias_lgk9 nx_hll_bias_lgk10 nx_hll_log2_ppm nx_hll_bias_correct nx_hll_bias_table_n ↻ nx_hll_bias_table_get ↻ nx_mulshl_div_i64 nx_i128_alloc

structs

none

consts

59const NX_OD_LCG_A: i64 = 1103515245
60const NX_OD_LCG_C: i64 = 12345
61const NX_OD_LCG_MOD: i64 = 0x7FFFFFFF

functions

43func iabs_od(x: i64) -> i64
called by 1: main
48func write_bod(buf: *u8, value: i64) -> i64
called by 1: main
63func main() -> i64