_gpu_dxg_r4c_pq_recon.nx source

1// _gpu_dxg_r4c_pq_recon.nx -- SOVEREIGN-GPU ladder R4c RECON (create a GPU PAGING QUEUE on the 5080). 2// 3// LX_DXCREATEPAGINGQUEUE (nr=0x07) creates the WDDM residency-manager object work is paged against, and 4// returns a paging_queue handle + a sync_object handle + a fence CPU virtual address (a real mmap'd page). 5// It should be tractable with just a device handle + priority=NORMAL(0). Best-guess struct: 6// d3dkmt_createpagingqueue: device @0 (in); priority @4 (in, 0=NORMAL); paging_queue @8 (OUT); 7// sync_object @12 (OUT); fence_cpu_virtual_address @16 (u64 OUT); physical_adapter_index @24 (in). ~32B 8// No uapi header -> discover live: sweep sizes for nr=0x07 (device@0, priority@4=0), and on ret==0 DUMP 9// the slots so the OUT handles + fence VA are located. raw syscalls only. No log writes. license_tier: ORIGINAL 10import "nx_syscalls.nx" 11 12const ENUM2_CODE: i64 = 0xC0104714 13const QAI_CODE: i64 = 0xC0184709 14const OAFL_CODE: i64 = 0xC00C4701 15const CDEV_CODE: i64 = 0xC0404702 16 17func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 18func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 19func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 20func iowr(nr: i64, size: i64) -> i64 { return (3 << 30) | ((size & 0x3fff) << 16) | (0x47 << 8) | (nr & 0xff) } 21func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) } 22func rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] } 23 24func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64 { 25 let priv: *u8 = sys_mmap(64); var zz: i64 = 0; while zz < 64 { priv[zz] = 0 as u8; zz = zz + 1 } 26 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 27 let h: *i64 = (req as i64 + 0) as *i64; h[0] = (handle & 0xffffffff) | ((qtype & 0xffffffff) << 32) 28 let pd: *i64 = (req as i64 + 8) as *i64; pd[0] = priv as i64 29 let pds: *i64 = (req as i64 + 16) as *i64; pds[0] = psize & 0xffffffff 30 let ret: i64 = sys_ioctl(fd, QAI_CODE, req as i64); outv[0] = rd32(priv, 0); return ret 31} 32func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64 { 33 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 34 let lo: *i64 = (req as i64 + 0) as *i64; lo[0] = (luid_lo & 0xffffffff) | ((luid_hi & 0xffffffff) << 32) 35 let ret: i64 = sys_ioctl(fd, OAFL_CODE, req as i64); outh[0] = rd32(req, 8); return ret 36} 37func create_device(fd: i64, adapter: i64, outd: *i64) -> i64 { 38 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 39 let a0: *i64 = (buf as i64) as *i64; a0[0] = adapter & 0xffffffff 40 let ret: i64 = sys_ioctl(fd, CDEV_CODE, buf as i64); outd[0] = rd32(buf, 12); return ret 41} 42 43func main() -> i64 { 44 p("=== R4c RECON: LX_DXCREATEPAGINGQUEUE (nr=0x07) on the 5080 device ===\n" as *u8) 45 let fd: i64 = sys_openat_rd("/dev/dxg" as *u8) 46 if fd < 0 { p("open(/dev/dxg) failed\n" as *u8); sys_exit(1); return 1 } 47 let ainfo: *u8 = sys_mmap(4096); var z: i64 = 0; while z < 4096 { ainfo[z] = 0 as u8; z = z + 1 } 48 let ereq: *u8 = sys_mmap(64); ereq[0] = 8 as u8; let r8: *i64 = (ereq as i64 + 8) as *i64; r8[0] = ainfo as i64 49 sys_ioctl(fd, ENUM2_CODE, ereq as i64); let nc: i64 = rd32(ereq, 0) 50 let v: *i64 = sys_mmap(16); var disc_lo: i64 = 0; var disc_hi: i64 = 0 51 var ai: i64 = 0 52 while ai < nc { 53 let base: i64 = ai * 20; let eh: i64 = rd32(ainfo, base) 54 let qret: i64 = query_type(fd, eh, 15, 4, v); let t: i64 = v[0] 55 if qret == 0 { if ((t>>4)&1) == 1 { if ((t>>2)&1) == 0 { disc_lo = rd32(ainfo, base+4); disc_hi = rd32(ainfo, base+8) } } } 56 ai = ai + 1 57 } 58 let ah: *i64 = sys_mmap(16); open_from_luid(fd, disc_lo, disc_hi, ah) 59 let dh: *i64 = sys_mmap(16); let dr: i64 = create_device(fd, ah[0], dh) 60 p(" device_create ret=" as *u8); n(dr); p(" device=" as *u8); x(dh[0]); p("\n" as *u8) 61 62 p("\n-- size sweep for nr=0x07 (device@0, priority@4=0). ret==0 = tractable rung --\n" as *u8) 63 let sizes: *i64 = sys_mmap(256) 64 sizes[0]=24; sizes[1]=28; sizes[2]=32; sizes[3]=36; sizes[4]=40; sizes[5]=48; sizes[6]=56; sizes[7]=0 65 var si: i64 = 0 66 while sizes[si] != 0 { 67 let sz: i64 = sizes[si] 68 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 69 let d0: *i64 = (buf as i64) as *i64; d0[0] = dh[0] & 0xffffffff // device @0; priority @4 = 0 70 let code: i64 = iowr(7, sz) 71 let ret: i64 = sys_ioctl(fd, code, buf as i64) 72 p(" size=" as *u8); n(sz); p(" code=" as *u8); x(code); p(" ret=" as *u8); n(ret) 73 if ret == 0 { 74 p("\n DUMP u32@8(pq)=" as *u8); x(rd32(buf,8)); p(" u32@12(sync)=" as *u8); x(rd32(buf,12)) 75 p(" u64@16(fenceVA)=" as *u8); x(rd64(buf,16)); p(" u64@24=" as *u8); x(rd64(buf,24)) 76 } 77 if ret != 0 - 25 { if ret != 0 { p(" <- recognized-but-error" as *u8) } } 78 p("\n" as *u8) 79 si = si + 1 80 } 81 sys_close(fd) 82 p("=== R4c PQ RECON DONE ===\n" as *u8) 83 return 0 84}