_gpu_dxg_r4d_alloc.nx source

1// _gpu_dxg_r4d_alloc.nx -- SOVEREIGN-GPU ladder R4d ATTEMPT: real UMD-less EXISTINGHEAP allocation on the 5080. 2// 3// Ground-truth layout (WSL2-Linux-Kernel d3dkmthk.h, VERIFIED against runtime fault-probes: device@0, 4// alloc_count@44, allocation_info@48 all confirmed; entry priv_drv_data_size@24 fault reconciled): 5// d3dkmt_createallocation (72B): device@0; reserved@12; private_runtime_data@16; private_runtime_data_size@24; 6// standard_allocation/priv_drv_data@32 (union); priv_drv_data_size@40; alloc_count@44; allocation_info@48; 7// flags@56 (createallocationflags: standard_allocation=bit16=0x10000, existing_sysmem=bit5=0x20); 8// private_runtime_resource_handle@64. 9// d3dkmt_createstandardallocation (24B): type@0 (EXISTINGHEAP=1); reserved@4; existing_heap.size@8 (u64); flags@16. 10// d3dddi_allocationinfo2 (natural-aligned 96B): allocation@0 (OUT); sysmem@8 (in, the existing heap mem); 11// priv_drv_data@16; priv_drv_data_size@24; vidpn_source_id@28; flags@32; gpu_virtual_address@40 (OUT); ... 12// Try flag combos {standard_allocation, standard_allocation|existing_sysmem} x size {4096}; print ret + the OUT 13// allocation handle (entry@0) + gpu_virtual_address (entry@40). raw syscalls only. No log writes. license_tier: ORIGINAL 14import "nx_syscalls.nx" 15 16const ENUM2_CODE: i64 = 0xC0104714 17const QAI_CODE: i64 = 0xC0184709 18const OAFL_CODE: i64 = 0xC00C4701 19const CDEV_CODE: i64 = 0xC0404702 20const CALLOC_CODE: i64 = 0xC0484706 21 22func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 23func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 24func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 25func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) } 26func rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] } 27func setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 } 28func setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 } 29 30func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64 { 31 let priv: *u8 = sys_mmap(64); var zz: i64 = 0; while zz < 64 { priv[zz] = 0 as u8; zz = zz + 1 } 32 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 33 let h: *i64 = (req as i64 + 0) as *i64; h[0] = (handle & 0xffffffff) | ((qtype & 0xffffffff) << 32) 34 let pd: *i64 = (req as i64 + 8) as *i64; pd[0] = priv as i64 35 let pds: *i64 = (req as i64 + 16) as *i64; pds[0] = psize & 0xffffffff 36 let ret: i64 = sys_ioctl(fd, QAI_CODE, req as i64); outv[0] = rd32(priv, 0); return ret 37} 38func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64 { 39 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 40 let lo: *i64 = (req as i64 + 0) as *i64; lo[0] = (luid_lo & 0xffffffff) | ((luid_hi & 0xffffffff) << 32) 41 let ret: i64 = sys_ioctl(fd, OAFL_CODE, req as i64); outh[0] = rd32(req, 8); return ret 42} 43func create_device(fd: i64, adapter: i64, outd: *i64) -> i64 { 44 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 45 setu32(buf, 0, adapter & 0xffffffff) 46 let ret: i64 = sys_ioctl(fd, CDEV_CODE, buf as i64); outd[0] = rd32(buf, 12); return ret 47} 48 49// build + fire an EXISTINGHEAP standard allocation. returns ret; OUT alloc handle -> outa[0], gpu_va -> outva[0]. 50func try_alloc(fd: i64, device: i64, flagval: i64, heapsize: i64, sysmem: *u8, outa: *i64, outva: *i64) -> i64 { 51 // descriptor (24B) 52 let desc: *u8 = sys_mmap(64); var dz: i64 = 0; while dz < 64 { desc[dz] = 0 as u8; dz = dz + 1 } 53 setu32(desc, 0, 1) // type = EXISTINGHEAP 54 setu64(desc, 8, heapsize) // existing_heap.size 55 // entry (96B, natural-aligned) 56 let entry: *u8 = sys_mmap(256); var ez: i64 = 0; while ez < 256 { entry[ez] = 0 as u8; ez = ez + 1 } 57 setu64(entry, 8, sysmem as i64) // sysmem @8 58 // global (72B) 59 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 60 setu32(buf, 0, device & 0xffffffff) // device @0 61 setu64(buf, 32, desc as i64) // standard_allocation @32 62 setu32(buf, 40, 24) // priv_drv_data_size @40 = sizeof(createstandardallocation) 63 setu32(buf, 44, 1) // alloc_count @44 64 setu64(buf, 48, entry as i64) // allocation_info @48 65 setu32(buf, 56, flagval) // flags @56 66 let ret: i64 = sys_ioctl(fd, CALLOC_CODE, buf as i64) 67 outa[0] = rd32(entry, 0); outva[0] = rd64(entry, 40); return ret 68} 69 70func main() -> i64 { 71 p("=== R4d ATTEMPT: EXISTINGHEAP standard allocation on the 5080 (ground-truth layout) ===\n" as *u8) 72 let fd: i64 = sys_openat_rd("/dev/dxg" as *u8) 73 if fd < 0 { p("open(/dev/dxg) failed\n" as *u8); sys_exit(1); return 1 } 74 let ainfo: *u8 = sys_mmap(4096); var z: i64 = 0; while z < 4096 { ainfo[z] = 0 as u8; z = z + 1 } 75 let ereq: *u8 = sys_mmap(64); ereq[0] = 8 as u8; let r8: *i64 = (ereq as i64 + 8) as *i64; r8[0] = ainfo as i64 76 sys_ioctl(fd, ENUM2_CODE, ereq as i64); let nc: i64 = rd32(ereq, 0) 77 let v: *i64 = sys_mmap(16); var disc_lo: i64 = 0; var disc_hi: i64 = 0 78 var ai: i64 = 0 79 while ai < nc { 80 let base: i64 = ai * 20; let eh: i64 = rd32(ainfo, base) 81 let qret: i64 = query_type(fd, eh, 15, 4, v); let t: i64 = v[0] 82 if qret == 0 { if ((t>>4)&1) == 1 { if ((t>>2)&1) == 0 { disc_lo = rd32(ainfo, base+4); disc_hi = rd32(ainfo, base+8) } } } 83 ai = ai + 1 84 } 85 let ah: *i64 = sys_mmap(16); open_from_luid(fd, disc_lo, disc_hi, ah) 86 let dh: *i64 = sys_mmap(16); create_device(fd, ah[0], dh); let device: i64 = dh[0] 87 p(" device=" as *u8); x(device); p("\n\n" as *u8) 88 89 let sysmem: *u8 = sys_mmap(4096); var sz: i64 = 0; while sz < 4096 { sysmem[sz] = 0 as u8; sz = sz + 1 } 90 let oa: *i64 = sys_mmap(16); let ova: *i64 = sys_mmap(16) 91 92 // flag combos: bit16 standard_allocation (0x10000); + bit5 existing_sysmem (0x20) 93 let flags: *i64 = sys_mmap(64); flags[0]=0x10000; flags[1]=0x10020; flags[2]=0x20; flags[3]= 0 - 1 94 var fi: i64 = 0 95 while flags[fi] != (0 - 1) { 96 let fv: i64 = flags[fi] 97 let r: i64 = try_alloc(fd, device, fv, 4096, sysmem, oa, ova) 98 p(" flags=" as *u8); x(fv); p(" -> ret=" as *u8); n(r); p(" alloc_handle=" as *u8); x(oa[0]); p(" gpu_va=" as *u8); x(ova[0]) 99 if r == 0 { if oa[0] != 0 { p(" <== REAL ALLOCATION!!" as *u8) } } 100 p("\n" as *u8) 101 fi = fi + 1 102 } 103 sys_close(fd) 104 p("=== R4d ATTEMPT DONE ===\n" as *u8) 105 return 0 106}