_gpu_dxg_r4d_probe3.nx source

1// _gpu_dxg_r4d_probe3.nx -- SOVEREIGN-GPU ladder R4d PROBE pass 3: characterize the d3dkmt_allocationinfo2 2// entry. Skeleton mapped: device@0, alloc_count@44, allocation_info@48 (ptr to entry array). A ZEROED entry 3// -> -75 (EOVERFLOW = the host rejects an empty allocation descriptor). Here we set each candidate field 4// inside the entry to a size-like 0x1000 (one at a time) and watch where the ret leaves -75 -- locating the 5// entry's size/flags/priv-data fields so the focused descriptor-build session is fully prepared. 6// raw syscalls only. No log writes. license_tier: ORIGINAL 7import "nx_syscalls.nx" 8 9const ENUM2_CODE: i64 = 0xC0104714 10const QAI_CODE: i64 = 0xC0184709 11const OAFL_CODE: i64 = 0xC00C4701 12const CDEV_CODE: i64 = 0xC0404702 13const CALLOC_CODE: i64 = 0xC0484706 14 15func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 16func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 17func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 18func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) } 19 20func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64 { 21 let priv: *u8 = sys_mmap(64); var zz: i64 = 0; while zz < 64 { priv[zz] = 0 as u8; zz = zz + 1 } 22 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 23 let h: *i64 = (req as i64 + 0) as *i64; h[0] = (handle & 0xffffffff) | ((qtype & 0xffffffff) << 32) 24 let pd: *i64 = (req as i64 + 8) as *i64; pd[0] = priv as i64 25 let pds: *i64 = (req as i64 + 16) as *i64; pds[0] = psize & 0xffffffff 26 let ret: i64 = sys_ioctl(fd, QAI_CODE, req as i64); outv[0] = rd32(priv, 0); return ret 27} 28func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64 { 29 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 30 let lo: *i64 = (req as i64 + 0) as *i64; lo[0] = (luid_lo & 0xffffffff) | ((luid_hi & 0xffffffff) << 32) 31 let ret: i64 = sys_ioctl(fd, OAFL_CODE, req as i64); outh[0] = rd32(req, 8); return ret 32} 33func create_device(fd: i64, adapter: i64, outd: *i64) -> i64 { 34 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 35 let a0: *i64 = (buf as i64) as *i64; a0[0] = adapter & 0xffffffff 36 let ret: i64 = sys_ioctl(fd, CDEV_CODE, buf as i64); outd[0] = rd32(buf, 12); return ret 37} 38// fire CREATEALLOCATION: device@0, alloc_count@44=1, allocation_info@48 -> entrybuf; entrybuf field@eoff = eval. 39func fire_entry(fd: i64, device: i64, entrybuf: *u8, eoff: i64, eval: i64) -> i64 { 40 var ez: i64 = 0; while ez < 256 { entrybuf[ez] = 0 as u8; ez = ez + 1 } 41 if eoff >= 0 { let ep: *i64 = (entrybuf as i64 + eoff) as *i64; ep[0] = eval } 42 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 43 let d0: *i64 = (buf as i64) as *i64; d0[0] = device & 0xffffffff 44 let acw: *u8 = (buf as i64 + 44) as *u8; acw[0]=1 as u8 // alloc_count@44 = 1 45 let aip: *i64 = (buf as i64 + 48) as *i64; aip[0] = entrybuf as i64 // allocation_info@48 46 return sys_ioctl(fd, CALLOC_CODE, buf as i64) 47} 48 49func main() -> i64 { 50 p("=== R4d PROBE-3: characterize d3dkmt_allocationinfo2 entry (baseline zeroed-entry = -75 EOVERFLOW) ===\n" as *u8) 51 let fd: i64 = sys_openat_rd("/dev/dxg" as *u8) 52 if fd < 0 { p("open(/dev/dxg) failed\n" as *u8); sys_exit(1); return 1 } 53 let ainfo: *u8 = sys_mmap(4096); var z: i64 = 0; while z < 4096 { ainfo[z] = 0 as u8; z = z + 1 } 54 let ereq: *u8 = sys_mmap(64); ereq[0] = 8 as u8; let r8: *i64 = (ereq as i64 + 8) as *i64; r8[0] = ainfo as i64 55 sys_ioctl(fd, ENUM2_CODE, ereq as i64); let nc: i64 = rd32(ereq, 0) 56 let v: *i64 = sys_mmap(16); var disc_lo: i64 = 0; var disc_hi: i64 = 0 57 var ai: i64 = 0 58 while ai < nc { 59 let base: i64 = ai * 20; let eh: i64 = rd32(ainfo, base) 60 let qret: i64 = query_type(fd, eh, 15, 4, v); let t: i64 = v[0] 61 if qret == 0 { if ((t>>4)&1) == 1 { if ((t>>2)&1) == 0 { disc_lo = rd32(ainfo, base+4); disc_hi = rd32(ainfo, base+8) } } } 62 ai = ai + 1 63 } 64 let ah: *i64 = sys_mmap(16); open_from_luid(fd, disc_lo, disc_hi, ah) 65 let dh: *i64 = sys_mmap(16); create_device(fd, ah[0], dh); let device: i64 = dh[0] 66 let entry: *u8 = sys_mmap(4096) 67 68 let base75: i64 = fire_entry(fd, device, entry, 0 - 1, 0) 69 p(" zeroed entry -> ret=" as *u8); n(base75); p("\n\n entry field@off set to 0x1000 -> ret (change from baseline = a meaningful field)\n" as *u8) 70 let offs: *i64 = sys_mmap(256) 71 offs[0]=0; offs[1]=8; offs[2]=16; offs[3]=24; offs[4]=32; offs[5]=36; offs[6]=40; offs[7]=44; offs[8]=48; offs[9]=56; offs[10]=64; offs[11]= 0 - 2 72 var oi: i64 = 0 73 while offs[oi] != (0 - 2) { 74 let o: i64 = offs[oi] 75 let r: i64 = fire_entry(fd, device, entry, o, 0x1000) 76 p(" entry@" as *u8); n(o); p(" : ret=" as *u8); n(r) 77 if r != base75 { p(" <== CHANGED" as *u8) } 78 p("\n" as *u8) 79 oi = oi + 1 80 } 81 sys_close(fd) 82 p("=== R4d PROBE-3 DONE ===\n" as *u8) 83 return 0 84}