_gpu_dxg_r4e_map_recon.nx source

1// _gpu_dxg_r4e_map_recon.nx -- SOVEREIGN-GPU ladder R4e RECON: map the R4d allocation to a GPU VA on the 5080. 2// Full chain: device -> paging queue (R4c) -> EXISTINGHEAP allocation (R4d) -> LX_DXMAPGPUVIRTUALADDRESS. 3// = _IOWR(0x47,0x0c,104) = 0xC068470C. struct d3dddi_mapgpuvirtualaddress (natural-aligned, total 104): 4// paging_queue@0; base_address@8; minimum_address@16; maximum_address@24; allocation@32; offset_in_pages@40; 5// size_in_pages@48; protection@56 (u64 bitfield: write=bit0); driver_protection@64; reserved0@72; reserved1@80; 6// **virtual_address@88 (OUT)**; **paging_fence_value@96 (OUT)**. Async: ret==0 assigns the VA immediately; 7// page-in completes when the paging queue fence reaches paging_fence_value. Try base=0 (auto-assign VA) with a 8// couple of max_address / protection values; print ret + va@88 + fence@96. raw syscalls only. license_tier: ORIGINAL 9import "nx_syscalls.nx" 10 11const ENUM2_CODE: i64 = 0xC0104714 12const QAI_CODE: i64 = 0xC0184709 13const OAFL_CODE: i64 = 0xC00C4701 14const CDEV_CODE: i64 = 0xC0404702 15const CPQ_CODE: i64 = 0xC0204707 16const CALLOC_CODE: i64 = 0xC0484706 17const MAPVA_CODE: i64 = 0xC068470C 18 19func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 20func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 21func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 22func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) } 23func rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] } 24func setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 } 25func setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 } 26 27func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64 { 28 let priv: *u8 = sys_mmap(64); var zz: i64 = 0; while zz < 64 { priv[zz] = 0 as u8; zz = zz + 1 } 29 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 30 let h: *i64 = (req as i64 + 0) as *i64; h[0] = (handle & 0xffffffff) | ((qtype & 0xffffffff) << 32) 31 let pd: *i64 = (req as i64 + 8) as *i64; pd[0] = priv as i64 32 let pds: *i64 = (req as i64 + 16) as *i64; pds[0] = psize & 0xffffffff 33 let ret: i64 = sys_ioctl(fd, QAI_CODE, req as i64); outv[0] = rd32(priv, 0); return ret 34} 35func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64 { 36 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 37 let lo: *i64 = (req as i64 + 0) as *i64; lo[0] = (luid_lo & 0xffffffff) | ((luid_hi & 0xffffffff) << 32) 38 let ret: i64 = sys_ioctl(fd, OAFL_CODE, req as i64); outh[0] = rd32(req, 8); return ret 39} 40func create_device(fd: i64, adapter: i64, outd: *i64) -> i64 { 41 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 42 setu32(buf, 0, adapter & 0xffffffff) 43 let ret: i64 = sys_ioctl(fd, CDEV_CODE, buf as i64); outd[0] = rd32(buf, 12); return ret 44} 45func create_pq(fd: i64, device: i64, outpq: *i64) -> i64 { 46 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 47 setu32(buf, 0, device & 0xffffffff) 48 let ret: i64 = sys_ioctl(fd, CPQ_CODE, buf as i64); outpq[0] = rd32(buf, 8); return ret 49} 50func alloc_eh(fd: i64, device: i64, sysmem: *u8, outh: *i64) -> i64 { 51 let desc: *u8 = sys_mmap(64); var dz: i64 = 0; while dz < 64 { desc[dz] = 0 as u8; dz = dz + 1 } 52 setu32(desc, 0, 1); setu64(desc, 8, 65536) 53 let entry: *u8 = sys_mmap(256); var ez: i64 = 0; while ez < 256 { entry[ez] = 0 as u8; ez = ez + 1 } 54 setu64(entry, 8, sysmem as i64) 55 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 56 setu32(buf, 0, device & 0xffffffff); setu64(buf, 32, desc as i64); setu32(buf, 40, 0) 57 setu32(buf, 44, 1); setu64(buf, 48, entry as i64); setu32(buf, 56, 0x10020) 58 let ret: i64 = sys_ioctl(fd, CALLOC_CODE, buf as i64); outh[0] = rd32(entry, 0); return ret 59} 60// map allocation -> GPU VA. OUT va@88 -> outva[0], fence@96 -> outf[0]. 61func map_va(fd: i64, pq: i64, alloc: i64, maxa: i64, sizepages: i64, prot: i64, outva: *i64, outf: *i64) -> i64 { 62 let buf: *u8 = sys_mmap(256); var bz: i64 = 0; while bz < 256 { buf[bz] = 0 as u8; bz = bz + 1 } 63 setu32(buf, 0, pq & 0xffffffff) // paging_queue @0 64 setu64(buf, 8, 0) // base_address @8 = 0 (auto-assign) 65 setu64(buf, 16, 0) // minimum_address @16 66 setu64(buf, 24, maxa) // maximum_address @24 67 setu32(buf, 32, alloc & 0xffffffff) // allocation @32 68 setu64(buf, 40, 0) // offset_in_pages @40 69 setu64(buf, 48, sizepages) // size_in_pages @48 70 setu64(buf, 56, prot) // protection @56 (write=bit0) 71 let ret: i64 = sys_ioctl(fd, MAPVA_CODE, buf as i64) 72 outva[0] = rd64(buf, 88); outf[0] = rd64(buf, 96); return ret 73} 74 75func main() -> i64 { 76 p("=== R4e RECON: map the R4d allocation to a GPU VA (full chain) ===\n" as *u8) 77 let fd: i64 = sys_openat_rd("/dev/dxg" as *u8) 78 if fd < 0 { p("open(/dev/dxg) failed\n" as *u8); sys_exit(1); return 1 } 79 let ainfo: *u8 = sys_mmap(4096); var z: i64 = 0; while z < 4096 { ainfo[z] = 0 as u8; z = z + 1 } 80 let ereq: *u8 = sys_mmap(64); ereq[0] = 8 as u8; let r8: *i64 = (ereq as i64 + 8) as *i64; r8[0] = ainfo as i64 81 sys_ioctl(fd, ENUM2_CODE, ereq as i64); let nc: i64 = rd32(ereq, 0) 82 let v: *i64 = sys_mmap(16); var disc_lo: i64 = 0; var disc_hi: i64 = 0 83 var ai: i64 = 0 84 while ai < nc { 85 let base: i64 = ai * 20; let eh: i64 = rd32(ainfo, base) 86 let qret: i64 = query_type(fd, eh, 15, 4, v); let t: i64 = v[0] 87 if qret == 0 { if ((t>>4)&1) == 1 { if ((t>>2)&1) == 0 { disc_lo = rd32(ainfo, base+4); disc_hi = rd32(ainfo, base+8) } } } 88 ai = ai + 1 89 } 90 let ah: *i64 = sys_mmap(16); open_from_luid(fd, disc_lo, disc_hi, ah) 91 let dh: *i64 = sys_mmap(16); create_device(fd, ah[0], dh); let device: i64 = dh[0] 92 let pqh: *i64 = sys_mmap(16); let pqr: i64 = create_pq(fd, device, pqh); let pq: i64 = pqh[0] 93 let sysmem: *u8 = sys_mmap(65536); var sz: i64 = 0; while sz < 65536 { sysmem[sz] = 0 as u8; sz = sz + 1 } 94 let alh: *i64 = sys_mmap(16); let alr: i64 = alloc_eh(fd, device, sysmem, alh); let alloc: i64 = alh[0] 95 p(" device=" as *u8); x(device); p(" pq(ret=" as *u8); n(pqr); p(")=" as *u8); x(pq); p(" alloc(ret=" as *u8); n(alr); p(")=" as *u8); x(alloc); p("\n" as *u8) 96 97 let ova: *i64 = sys_mmap(16); let ofv: *i64 = sys_mmap(16) 98 p(" map (max=0x10000000000, 16pg, prot=write):" as *u8); let r1: i64 = map_va(fd, pq, alloc, 0x10000000000, 16, 1, ova, ofv); p(" ret=" as *u8); n(r1); p(" gpu_va=" as *u8); x(ova[0]); p(" fence=" as *u8); n(ofv[0]); if r1==0 { if ova[0]!=0 { p(" <== MAPPED!" as *u8) } } p("\n" as *u8) 99 p(" map (max=0, 16pg, prot=write):" as *u8); let r2: i64 = map_va(fd, pq, alloc, 0, 16, 1, ova, ofv); p(" ret=" as *u8); n(r2); p(" gpu_va=" as *u8); x(ova[0]); p(" fence=" as *u8); n(ofv[0]); if r2==0 { if ova[0]!=0 { p(" <== MAPPED!" as *u8) } } p("\n" as *u8) 100 p(" map (max=0x10000000000, 16pg, prot=0) :" as *u8); let r3: i64 = map_va(fd, pq, alloc, 0x10000000000, 16, 0, ova, ofv); p(" ret=" as *u8); n(r3); p(" gpu_va=" as *u8); x(ova[0]); p(" fence=" as *u8); n(ofv[0]); if r3==0 { if ova[0]!=0 { p(" <== MAPPED!" as *u8) } } p("\n" as *u8) 101 sys_close(fd) 102 p("=== R4e MAP RECON DONE ===\n" as *u8) 103 return 0 104}