_gpu_dxg_r4e_recon.nx source

1// _gpu_dxg_r4e_recon.nx -- SOVEREIGN-GPU ladder R4e RECON: reserve GPU virtual-address space on the 5080. 2// 3// LX_DXRESERVEGPUVIRTUALADDRESS = _IOWR(0x47,0x08,72) = 0xC0484708 (header-derived, natural-aligned, VERIFIED total 72). 4// struct d3dddi_reservegpuvirtualaddress: adapter@0 (in; or paging-queue handle); base_address@8; minimum_address@16; 5// maximum_address@24; size@32; reservation_type@40 (enum: NO_ACCESS=0/ZERO=1/NO_COMMIT=2); driver_protection@48; 6// **virtual_address@56 (OUT)**; paging_fence_value@64. Synchronous (no fence wait per ioctl.c). 7// Try a few (max_address, size, reservation_type) combos with the discrete adapter handle; print ret + the 8// reserved GPU virtual_address@56. ret==0 + non-zero VA = a real GPU VA reservation. raw syscalls only. license_tier: ORIGINAL 9import "nx_syscalls.nx" 10 11const ENUM2_CODE: i64 = 0xC0104714 12const QAI_CODE: i64 = 0xC0184709 13const OAFL_CODE: i64 = 0xC00C4701 14const CDEV_CODE: i64 = 0xC0404702 15const RESVA_CODE: i64 = 0xC0484708 16 17func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 18func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 19func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 20func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) } 21func rd64(buf: *u8, off: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; return q[0] } 22func setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 } 23func setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 } 24 25func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64 { 26 let priv: *u8 = sys_mmap(64); var zz: i64 = 0; while zz < 64 { priv[zz] = 0 as u8; zz = zz + 1 } 27 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 28 let h: *i64 = (req as i64 + 0) as *i64; h[0] = (handle & 0xffffffff) | ((qtype & 0xffffffff) << 32) 29 let pd: *i64 = (req as i64 + 8) as *i64; pd[0] = priv as i64 30 let pds: *i64 = (req as i64 + 16) as *i64; pds[0] = psize & 0xffffffff 31 let ret: i64 = sys_ioctl(fd, QAI_CODE, req as i64); outv[0] = rd32(priv, 0); return ret 32} 33func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64 { 34 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 35 let lo: *i64 = (req as i64 + 0) as *i64; lo[0] = (luid_lo & 0xffffffff) | ((luid_hi & 0xffffffff) << 32) 36 let ret: i64 = sys_ioctl(fd, OAFL_CODE, req as i64); outh[0] = rd32(req, 8); return ret 37} 38// reserve GPU VA; OUT virtual_address@56 -> outva[0]. 39func reserve(fd: i64, code: i64, adapter: i64, mina: i64, maxa: i64, size: i64, rtype: i64, outva: *i64) -> i64 { 40 let buf: *u8 = sys_mmap(256); var bz: i64 = 0; while bz < 256 { buf[bz] = 0 as u8; bz = bz + 1 } 41 setu32(buf, 0, adapter & 0xffffffff) // adapter @0 42 setu64(buf, 8, 0) // base_address @8 = 0 43 setu64(buf, 16, mina) // minimum_address @16 44 setu64(buf, 24, maxa) // maximum_address @24 45 setu64(buf, 32, size) // size @32 46 setu32(buf, 40, rtype) // reservation_type @40 47 let ret: i64 = sys_ioctl(fd, code, buf as i64) 48 outva[0] = rd64(buf, 56); return ret 49} 50 51func main() -> i64 { 52 p("=== R4e RECON: LX_DXRESERVEGPUVIRTUALADDRESS -> reserve GPU VA space on the 5080 ===\n" as *u8) 53 let fd: i64 = sys_openat_rd("/dev/dxg" as *u8) 54 if fd < 0 { p("open(/dev/dxg) failed\n" as *u8); sys_exit(1); return 1 } 55 let ainfo: *u8 = sys_mmap(4096); var z: i64 = 0; while z < 4096 { ainfo[z] = 0 as u8; z = z + 1 } 56 let ereq: *u8 = sys_mmap(64); ereq[0] = 8 as u8; let r8: *i64 = (ereq as i64 + 8) as *i64; r8[0] = ainfo as i64 57 sys_ioctl(fd, ENUM2_CODE, ereq as i64); let nc: i64 = rd32(ereq, 0) 58 let v: *i64 = sys_mmap(16); var disc_lo: i64 = 0; var disc_hi: i64 = 0 59 var ai: i64 = 0 60 while ai < nc { 61 let base: i64 = ai * 20; let eh: i64 = rd32(ainfo, base) 62 let qret: i64 = query_type(fd, eh, 15, 4, v); let t: i64 = v[0] 63 if qret == 0 { if ((t>>4)&1) == 1 { if ((t>>2)&1) == 0 { disc_lo = rd32(ainfo, base+4); disc_hi = rd32(ainfo, base+8) } } } 64 ai = ai + 1 65 } 66 let ah: *i64 = sys_mmap(16); open_from_luid(fd, disc_lo, disc_hi, ah); let adapter: i64 = ah[0] 67 p(" adapter=" as *u8); x(adapter); p("\n (min,max,size,rtype) -> ret : reserved_gpu_va\n" as *u8) 68 69 let ova: *i64 = sys_mmap(16) 70 // combos: vary maximum_address + reservation_type. size=64KB. 71 p(" (0, 0x10000000000, 64K, 0) :" as *u8); let r1: i64 = reserve(fd, RESVA_CODE, adapter, 0, 0x10000000000, 65536, 0, ova); p(" ret=" as *u8); n(r1); p(" va=" as *u8); x(ova[0]); if r1==0 { if ova[0]!=0 { p(" <== RESERVED!" as *u8) } } p("\n" as *u8) 72 p(" (0, 0x1000000000, 64K, 0) :" as *u8); let r2: i64 = reserve(fd, RESVA_CODE, adapter, 0, 0x1000000000, 65536, 0, ova); p(" ret=" as *u8); n(r2); p(" va=" as *u8); x(ova[0]); if r2==0 { if ova[0]!=0 { p(" <== RESERVED!" as *u8) } } p("\n" as *u8) 73 p(" (0, 0x10000000000, 64K, 1) :" as *u8); let r3: i64 = reserve(fd, RESVA_CODE, adapter, 0, 0x10000000000, 65536, 1, ova); p(" ret=" as *u8); n(r3); p(" va=" as *u8); x(ova[0]); if r3==0 { if ova[0]!=0 { p(" <== RESERVED!" as *u8) } } p("\n" as *u8) 74 p(" (0, 0, 64K, 0) :" as *u8); let r4: i64 = reserve(fd, RESVA_CODE, adapter, 0, 0, 65536, 0, ova); p(" ret=" as *u8); n(r4); p(" va=" as *u8); x(ova[0]); p("\n" as *u8) 75 sys_close(fd) 76 p("=== R4e RECON DONE ===\n" as *u8) 77 return 0 78}