_gpu_dxg_r4g_sw_recon.nx source

1// _gpu_dxg_r4g_sw_recon.nx -- R4g RECON: signal+wait a monitored-fence sync object from CPU. 2// CREATESYNCHRONIZATIONOBJECT size 96 = 0xC0604710 (type@8=5 monitored fence -> sync_object@88, recon-pinned). 3// SIGNALSYNCHRONIZATIONOBJECTFROMCPU nr=0x31: device@0,object_count@4,objects@8(ptr),fence_values@16(ptr),flags@24. 4// WAITFORSYNCHRONIZATIONOBJECTFROMCPU nr=0x3a: device@0,object_count@4,objects@8,fence_values@16,async_event@24,flags@32. 5// Sizes header-naive -> size-sweep both. Plan: create fence -> signal to value 5 -> wait for value 5 (should return 0). 6// raw syscalls only. No log writes. license_tier: ORIGINAL 7import "nx_syscalls.nx" 8 9const ENUM2_CODE: i64 = 0xC0104714 10const QAI_CODE: i64 = 0xC0184709 11const OAFL_CODE: i64 = 0xC00C4701 12const CDEV_CODE: i64 = 0xC0404702 13const CSO_CODE: i64 = 0xC0604710 14 15func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 16func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 17func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 18func iowr(nr: i64, size: i64) -> i64 { return (3 << 30) | ((size & 0x3fff) << 16) | (0x47 << 8) | (nr & 0xff) } 19func rd32(buf: *u8, off: i64) -> i64 { return (buf[off] as i64)|((buf[off+1] as i64)<<8)|((buf[off+2] as i64)<<16)|((buf[off+3] as i64)<<24) } 20func setu32(buf: *u8, off: i64, val: i64) -> i64 { let w: *u8 = (buf as i64 + off) as *u8; w[0]=(val&0xff) as u8; w[1]=((val>>8)&0xff) as u8; w[2]=((val>>16)&0xff) as u8; w[3]=((val>>24)&0xff) as u8; return 0 } 21func setu64(buf: *u8, off: i64, val: i64) -> i64 { let q: *i64 = (buf as i64 + off) as *i64; q[0]=val; return 0 } 22 23func query_type(fd: i64, handle: i64, qtype: i64, psize: i64, outv: *i64) -> i64 { 24 let priv: *u8 = sys_mmap(64); var zz: i64 = 0; while zz < 64 { priv[zz] = 0 as u8; zz = zz + 1 } 25 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 26 let h: *i64 = (req as i64 + 0) as *i64; h[0] = (handle & 0xffffffff) | ((qtype & 0xffffffff) << 32) 27 let pd: *i64 = (req as i64 + 8) as *i64; pd[0] = priv as i64 28 let pds: *i64 = (req as i64 + 16) as *i64; pds[0] = psize & 0xffffffff 29 let ret: i64 = sys_ioctl(fd, QAI_CODE, req as i64); outv[0] = rd32(priv, 0); return ret 30} 31func open_from_luid(fd: i64, luid_lo: i64, luid_hi: i64, outh: *i64) -> i64 { 32 let req: *u8 = sys_mmap(64); var y: i64 = 0; while y < 64 { req[y] = 0 as u8; y = y + 1 } 33 let lo: *i64 = (req as i64 + 0) as *i64; lo[0] = (luid_lo & 0xffffffff) | ((luid_hi & 0xffffffff) << 32) 34 let ret: i64 = sys_ioctl(fd, OAFL_CODE, req as i64); outh[0] = rd32(req, 8); return ret 35} 36func create_device(fd: i64, adapter: i64, outd: *i64) -> i64 { 37 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 38 setu32(buf, 0, adapter & 0xffffffff) 39 let ret: i64 = sys_ioctl(fd, CDEV_CODE, buf as i64); outd[0] = rd32(buf, 12); return ret 40} 41func create_mf(fd: i64, device: i64, outso: *i64) -> i64 { 42 let buf: *u8 = sys_mmap(512); var bz: i64 = 0; while bz < 512 { buf[bz] = 0 as u8; bz = bz + 1 } 43 setu32(buf, 0, device & 0xffffffff); setu32(buf, 8, 5) 44 let ret: i64 = sys_ioctl(fd, CSO_CODE, buf as i64); outso[0] = rd32(buf, 88); return ret 45} 46 47func main() -> i64 { 48 p("=== R4g RECON: monitored-fence CPU signal + wait ===\n" as *u8) 49 let fd: i64 = sys_openat_rd("/dev/dxg" as *u8) 50 if fd < 0 { p("open fail\n" as *u8); sys_exit(1); return 1 } 51 let ainfo: *u8 = sys_mmap(4096); var z: i64 = 0; while z < 4096 { ainfo[z] = 0 as u8; z = z + 1 } 52 let ereq: *u8 = sys_mmap(64); ereq[0] = 8 as u8; let r8: *i64 = (ereq as i64 + 8) as *i64; r8[0] = ainfo as i64 53 sys_ioctl(fd, ENUM2_CODE, ereq as i64); let nc: i64 = rd32(ereq, 0) 54 let v: *i64 = sys_mmap(16); var disc_lo: i64 = 0; var disc_hi: i64 = 0 55 var ai: i64 = 0 56 while ai < nc { 57 let base: i64 = ai * 20; let eh: i64 = rd32(ainfo, base) 58 let qret: i64 = query_type(fd, eh, 15, 4, v); let t: i64 = v[0] 59 if qret == 0 { if ((t>>4)&1) == 1 { if ((t>>2)&1) == 0 { disc_lo = rd32(ainfo, base+4); disc_hi = rd32(ainfo, base+8) } } } 60 ai = ai + 1 61 } 62 let ah: *i64 = sys_mmap(16); open_from_luid(fd, disc_lo, disc_hi, ah) 63 let dh: *i64 = sys_mmap(16); create_device(fd, ah[0], dh); let device: i64 = dh[0] 64 let soh: *i64 = sys_mmap(16); let cr: i64 = create_mf(fd, device, soh); let so: i64 = soh[0] 65 p(" device=" as *u8); x(device); p(" create_mf ret=" as *u8); n(cr); p(" sync_object=" as *u8); x(so); p("\n" as *u8) 66 67 // objects[1] and fence_values[1] arrays 68 let objs: *u8 = sys_mmap(64); setu32(objs, 0, so) 69 let vals: *u8 = sys_mmap(64); setu64(vals, 0, 5) // signal/wait to value 5 70 71 // ---- SIGNAL-from-CPU size sweep (nr=0x31) ---- 72 p(" SIGNAL nr=0x31 sweep:\n" as *u8) 73 let ss: *i64 = sys_mmap(64); ss[0]=24; ss[1]=28; ss[2]=32; ss[3]=0 74 var i1: i64 = 0 75 while ss[i1] != 0 { 76 let sz: i64 = ss[i1] 77 let buf: *u8 = sys_mmap(128); var bz: i64 = 0; while bz < 128 { buf[bz] = 0 as u8; bz = bz + 1 } 78 setu32(buf, 0, device & 0xffffffff); setu32(buf, 4, 1); setu64(buf, 8, objs as i64); setu64(buf, 16, vals as i64) 79 let r: i64 = sys_ioctl(fd, iowr(0x31, sz), buf as i64) 80 p(" size=" as *u8); n(sz); p(" ret=" as *u8); n(r); if r != 0-25 { p(" <-recognized" as *u8) } p("\n" as *u8) 81 i1 = i1 + 1 82 } 83 // ---- WAIT-from-CPU size sweep (nr=0x3a), sync (async_event=0) ---- 84 p(" WAIT nr=0x3a sweep (value 5, should return 0 since already signaled):\n" as *u8) 85 let ws: *i64 = sys_mmap(64); ws[0]=32; ws[1]=36; ws[2]=40; ws[3]=44; ws[4]=0 86 var i2: i64 = 0 87 while ws[i2] != 0 { 88 let sz: i64 = ws[i2] 89 let buf: *u8 = sys_mmap(128); var bz: i64 = 0; while bz < 128 { buf[bz] = 0 as u8; bz = bz + 1 } 90 setu32(buf, 0, device & 0xffffffff); setu32(buf, 4, 1); setu64(buf, 8, objs as i64); setu64(buf, 16, vals as i64) 91 let r: i64 = sys_ioctl(fd, iowr(0x3a, sz), buf as i64) 92 p(" size=" as *u8); n(sz); p(" ret=" as *u8); n(r); if r != 0-25 { p(" <-recognized" as *u8) } p("\n" as *u8) 93 i2 = i2 + 1 94 } 95 sys_close(fd) 96 p("=== R4g SW RECON DONE ===\n" as *u8) 97 return 0 98}