_gpu_dxg_r6_hwq.nx source

1// _gpu_dxg_r6_hwq.nx -- SOVEREIGN-GPU R6: make the real RTX 5080 EXECUTE via the HARDWARE-QUEUE path. 2// Now rides the CONSOLIDATED dxg device shim (nx_dxg) instead of inline-copying the control plane. 3// 4// HYPOTHESIS (grounded in the open WSL2-Linux-Kernel dxgkrnl ABI): R5a used LX_DXSUBMITCOMMAND (packet- 5// scheduling). Modern NVIDIA on WSL uses HARDWARE SCHEDULING -> packet-scheduled submit is ACCEPTED but never 6// dispatched. The HWS path = D3DKMTCreateHwQueue + D3DKMTSubmitCommandToHwQueue (in nx_dxg). CreateHwQueue 7// returns a MONITORED PROGRESS FENCE the GPU signals on completion -> a clean dispatch/exec signal. 8// RESULT (recorded): CreateHwQueue -EINVAL = host NVIDIA KMD rejects (needs proprietary priv_drv_data) -> the 9// dxg path is the proprietary-handshake dead-end; the sovereign route is the open-kernel-module/bare-metal path 10// on native-Linux/passthrough (see project-cuda-exceed-roadmap). NISHI-ONLY: we emit the raw pushbuffer; no 11// libcuda/Mesa. RISK: a malformed HW submit may TDR; WSL recovers. license_tier: ORIGINAL 12import "nx_syscalls.nx" 13import "nx_dxg.nx" 14 15func p(s: *u8) -> i64 { var nn: i64=0; while s[nn]!=(0 as u8){nn=nn+1} sys_write(1,s,nn); return 0 } 16func n(v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m;sys_write(1,"-" as *u8,1)}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48 as u8;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(1,bb,k); return 0 } 17func x(v: i64) -> i64 { p("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48 as u8;k=1}; while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 18 19func main() -> i64 { 20 p("=== SOVEREIGN-GPU R6: HARDWARE-QUEUE submit -> make the real 5080 dispatch+execute our pushbuffer (via nx_dxg shim) ===\n" as *u8) 21 let fd: i64 = dxg_open() 22 if fd < 0 { p("open fail\n" as *u8); sys_exit(1); return 1 } 23 let ainfo: *u8 = sys_mmap(4096) 24 let nc: i64 = dxg_enum(fd, ainfo) 25 let v: *i64 = sys_mmap(16); var disc_lo: i64 = 0; var disc_hi: i64 = 0 26 var ai: i64 = 0 27 while ai < nc { 28 let base: i64 = ai * 20; let eh: i64 = dxg_rd32(ainfo, base) 29 let qret: i64 = dxg_query_type(fd, eh, 15, 4, v); let t: i64 = v[0] 30 if qret == 0 { if ((t>>4)&1) == 1 { if ((t>>2)&1) == 0 { disc_lo = dxg_rd32(ainfo, base+4); disc_hi = dxg_rd32(ainfo, base+8) } } } 31 ai = ai + 1 32 } 33 let ah: *i64 = sys_mmap(16); dxg_open_from_luid(fd, disc_lo, disc_hi, ah) 34 let dh: *i64 = sys_mmap(16); dxg_create_device(fd, ah[0], dh); let device: i64 = dh[0] 35 let ch: *i64 = sys_mmap(16); dxg_create_ctx(fd, device, ch); let context: i64 = ch[0] 36 let pqh: *i64 = sys_mmap(16); let fvah: *i64 = sys_mmap(16); dxg_create_pq(fd, device, pqh, fvah); let pq: i64 = pqh[0] 37 38 let sm_pb: *u8 = sys_mmap(65536); var a1: i64 = 0; while a1 < 65536 { sm_pb[a1] = 0 as u8; a1 = a1 + 1 } 39 let sm_tg: *u8 = sys_mmap(65536); var a2: i64 = 0; while a2 < 65536 { sm_tg[a2] = 0 as u8; a2 = a2 + 1 } 40 let pbh: *i64 = sys_mmap(16); dxg_alloc_eh(fd, device, sm_pb, pbh); let pb_alloc: i64 = pbh[0] 41 let tgh: *i64 = sys_mmap(16); dxg_alloc_eh(fd, device, sm_tg, tgh); let tg_alloc: i64 = tgh[0] 42 let pbva: *i64 = sys_mmap(16); let dummy1: *i64 = sys_mmap(16); dxg_map_va(fd, pq, pb_alloc, pbva, dummy1); let pb_va: i64 = pbva[0] 43 let tgva: *i64 = sys_mmap(16); let dummy2: *i64 = sys_mmap(16); dxg_map_va(fd, pq, tg_alloc, tgva, dummy2); let tg_va: i64 = tgva[0] 44 let mf1: *i64 = sys_mmap(16); dxg_makeresident(fd, pq, pb_alloc, mf1) 45 let mf2: *i64 = sys_mmap(16); dxg_makeresident(fd, pq, tg_alloc, mf2) 46 p(" context=" as *u8); x(context); p(" pb_va=" as *u8); x(pb_va); p(" tg_va=" as *u8); x(tg_va); p("\n" as *u8) 47 48 let PAYLOAD: i64 = 0xCAFEBABE 49 dxg_setu32(sm_pb, 0, 0x20050017) 50 dxg_setu32(sm_pb, 4, tg_va & 0xffffffff) 51 dxg_setu32(sm_pb, 8, (tg_va >> 32) & 0xffffffff) 52 dxg_setu32(sm_pb, 12, PAYLOAD) 53 dxg_setu32(sm_pb, 16, 0) 54 dxg_setu32(sm_pb, 20, 0x1) 55 56 let hqh: *i64 = sys_mmap(16); let hfgva: *i64 = sys_mmap(16); let hfcva: *i64 = sys_mmap(16) 57 let hqret: i64 = dxg_create_hwqueue(fd, context, hqh, hfgva, hfcva); let hwqueue: i64 = hqh[0] 58 p(" CREATEHWQUEUE ret=" as *u8); n(hqret); p(" hwqueue=" as *u8); x(hwqueue); p(" fence_gpu_va=" as *u8); x(hfgva[0]); p(" fence_cpu_va=" as *u8); x(hfcva[0]); p("\n" as *u8) 59 60 if hqret == 0 { 61 if hwqueue != 0 { 62 let sr: i64 = dxg_submit_hwq(fd, hwqueue, pb_va, 24, 1) 63 p(" SUBMITCOMMANDTOHWQUEUE ret=" as *u8); n(sr); p("\n" as *u8) 64 var fence_done: i64 = 0 65 if hfcva[0] != 0 { 66 let fp: *i64 = hfcva[0] as *i64 67 var it: i64 = 0 68 while it < 200000000 { if fp[0] >= 1 { fence_done = 1; it = 200000000 } else { it = it + 1 } } 69 p(" progress_fence=" as *u8); x(fp[0]) 70 if fence_done == 1 { p(" (*** DISPATCHED + COMPLETED ***)" as *u8) } else { p(" (not signaled -- accepted but not run)" as *u8) } 71 p("\n" as *u8) 72 } 73 var it2: i64 = 0 74 while it2 < 100000000 { let w: i64 = dxg_rd32(sm_tg, 0); if w == PAYLOAD { it2 = 100000000 } else { it2 = it2 + 1 } } 75 let final: i64 = dxg_rd32(sm_tg, 0) 76 p(" target buffer (CPU read) = " as *u8); x(final); p(" expected=" as *u8); x(PAYLOAD); p("\n" as *u8) 77 if final == PAYLOAD { p(" *** THE RTX 5080 EXECUTED OUR SOVEREIGN PUSHBUFFER VIA HWQUEUE ***\n" as *u8) } 78 else { p(" (semaphore not observed -- see CreateHwQueue/submit/fence diagnostics above)\n" as *u8) } 79 } 80 } 81 if hqret != 0 { p(" (CreateHwQueue failed -- the host NVIDIA KMD needs proprietary priv_drv_data; dxg = the proprietary-handshake dead-end, see roadmap)\n" as *u8) } 82 sys_close(fd) 83 p("=== R6 DONE ===\n" as *u8) 84 return 0 85}