_gpu_run.nx source

1// _gpu_run.nx -- a SOVEREIGN rv64 runner with the GPU-class device ATTACHED (twin of 2// nx_boot_run_sov, dedicated to the GPU op-list driver so the shared nx_boot_run_sov stays 3// untouched). Loads an emitter-authored rv64 flat image, runs it on the Nishi-owned emu with the 4// virtio/nvme/nndev/mmu + the new GPU controller (rv64im_min_gpu @0x10007000) attached, and prints 5// the same "BOOTSOV verdict=GREEN" clean-halt marker the gate greps for. Sovereign: the emulator 6// IS the runtime, no qemu/gcc. license_tier: ORIGINAL 7import "rv64im_min_sim.nx" 8import "rv64im_min_csr.nx" 9import "rv64im_min_clint.nx" 10import "rv64im_min_uart.nx" 11import "rv64im_min_virtio.nx" 12import "rv64im_min_nvme.nx" 13import "rv64im_min_gpu.nx" 14 15const GR_MEM_BASE: i64 = 0x80000000 16const GR_MEM_SIZE: i64 = 65536 17const GR_TX_CAP: i64 = 4096 18const GR_MAX_STEPS: i64 = 100000 19 20func gr_p(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } 21func gr_fn(fd: i64, v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(fd,bb,k); return 0 } 22 23func main(argc: i64, argv: *i64) -> i64 { 24 var binp: *u8 = "runtime/_hdl_build/_gpu_dispatch.bin" as *u8 25 if argc >= 2 { binp = argv[1] as *u8 } 26 27 let lenp: *i64 = sys_mmap(16) as *i64 28 let img: *u8 = sys_read_file(binp, lenp) 29 let ilen: i64 = lenp[0] 30 if ilen <= 0 { gr_p("BOOTSOV verdict=RED reason=binary-missing\n" as *u8); sys_exit(1); return 1 } 31 32 let rf_storage: *i64 = (sys_mmap(8 * NX_RV64IM_RF_N_REGS)) as *i64 33 let csr_storage: *i64 = (sys_mmap(8 * NX_CSR_SLOT_N)) as *i64 34 let clint_storage: *i64 = (sys_mmap(8 * NX_CLINT_SLOT_N)) as *i64 35 let uart_storage: *i64 = (sys_mmap(8 * NX_UART_SLOT_N)) as *i64 36 let virtio_storage:*i64 = (sys_mmap(8 * NX_VIRTIO_SLOT_N)) as *i64 37 let vnet_storage: *i64 = (sys_mmap(8 * NX_VIRTIO_SLOT_N)) as *i64 38 let nvme_storage: *i64 = (sys_mmap(8 * NX_NVME_SLOT_N)) as *i64 39 let gpu_storage: *i64 = (sys_mmap(8 * NX_GPU_SLOT_N)) as *i64 40 let mem: *u8 = sys_mmap(GR_MEM_SIZE) 41 let tx_buf: *u8 = sys_mmap(GR_TX_CAP) 42 let rf: *NxRv64imRegfile = (sys_mmap(64)) as *NxRv64imRegfile 43 let csr: *NxRv64imCsrFile = (sys_mmap(64)) as *NxRv64imCsrFile 44 let clint: *NxClint = (sys_mmap(64)) as *NxClint 45 let uart: *NxUart = (sys_mmap(64)) as *NxUart 46 let virtio:*NxVirtioMmio = (sys_mmap(64)) as *NxVirtioMmio 47 let vnet: *NxVirtioMmio = (sys_mmap(64)) as *NxVirtioMmio 48 let nvme: *NxNvmeCtrl = (sys_mmap(64)) as *NxNvmeCtrl 49 let gpu: *NxGpu = (sys_mmap(64)) as *NxGpu 50 let sim: *NxRv64imSim = (sys_mmap(256)) as *NxRv64imSim 51 52 nx_rv64im_rf_init(rf, rf_storage) 53 nx_rv64im_csr_init(csr, csr_storage, 0) 54 nx_clint_init(clint, clint_storage) 55 nx_uart_init(uart, uart_storage, tx_buf, GR_TX_CAP) 56 nx_virtio_init(virtio, virtio_storage) 57 nx_virtio_init_net(vnet, vnet_storage) 58 nx_nvme_init(nvme, nvme_storage) 59 nx_gpu_init(gpu, gpu_storage) 60 nx_rv64im_sim_init(sim, rf, csr, clint, uart, GR_MEM_BASE, mem, GR_MEM_SIZE, 0) 61 nx_rv64im_sim_attach_virtio(sim, virtio) 62 nx_rv64im_sim_attach_virtio_net(sim, vnet) 63 nx_rv64im_sim_attach_nvme(sim, nvme) 64 nx_rv64im_sim_attach_gpu(sim, gpu) 65 66 var i: i64 = 0 67 while i < ilen { mem[i] = img[i]; i = i + 1 } 68 69 nx_rv64im_sim_run(sim, GR_MAX_STEPS) 70 71 let cnt: i64 = nx_uart_tx_count(uart) 72 gr_p("SOVEREIGN-EMU serial: " as *u8) 73 sys_write(1, tx_buf, cnt) 74 gr_p("\n" as *u8) 75 76 var ok: i64 = 0 77 if sim.halted == 1 { if sim.halt_code == 0 { ok = 1 } } 78 if ok == 1 { 79 gr_p("BOOTSOV verdict=GREEN (booted on the sovereign rv64 emu; clean finisher halt) steps=" as *u8); gr_fn(1, sim.steps); gr_p("\n" as *u8) 80 sys_exit(0); return 0 81 } 82 gr_p("BOOTSOV verdict=RED (no clean halt) halted=" as *u8); gr_fn(1, sim.halted); gr_p(" code=" as *u8); gr_fn(1, sim.halt_code); gr_p("\n" as *u8) 83 sys_exit(1) 84 return 1 85}