_self_host_simd_shift_test.nx source
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1// _self_host_simd_shift_test.nx -- vsll/vsrl/vsra for i16x16.
2// Critical: vsra must sign-extend negative lanes (the SIMD version
3// of the nxasm srai bug we just fixed). Returns case# on fail.
4
5import "nx_syscalls.nx"
6
7func main() -> i64 {
8 let a_raw: *u8 = sys_mmap(64)
9 let o_raw: *u8 = sys_mmap(64)
10 let a: *i64 = a_raw as *i64
11 let o: *i64 = o_raw as *i64
12
13 // Test 1: vsll by 2. a = [1,2,3,4, ...] << 2 = [4,8,12,16, ...]
14 // Max lane of input = 16, max of output = 64.
15 a[0] = 0x0004000300020001
16 a[1] = 0x0008000700060005
17 a[2] = 0x000c000b000a0009
18 a[3] = 0x0010000f000e000d
19 let d1: i64 = __simd_vsll_i16_x16(a as *i64, 2, o as *i64)
20 let r1: i64 = __simd_vreduce_max_i16_x16(o as *i64)
21 if r1 != 64 { return 1 }
22
23 // Test 2: vsrl by 1 with negative-valued lane. -2 = 0xFFFE.
24 // 0xFFFE >> 1 logical = 0x7FFF = 32767 (signed view).
25 a[0] = 0xFFFEFFFEFFFEFFFE // 4 lanes of -2 (or 0xFFFE)
26 a[1] = 0xFFFEFFFEFFFEFFFE
27 a[2] = 0xFFFEFFFEFFFEFFFE
28 a[3] = 0xFFFEFFFEFFFEFFFE
29 let d2: i64 = __simd_vsrl_i16_x16(a as *i64, 1, o as *i64)
30 let r2: i64 = __simd_vreduce_max_i16_x16(o as *i64)
31 if r2 != 32767 { return 2 }
32 // vreduce_min of all-same vector should also be 32767.
33 let r2b: i64 = __simd_vreduce_min_i16_x16(o as *i64)
34 if r2b != 32767 { return 12 }
35
36 // Test 3: vsra by 1 with negative-valued lane. -2 >> 1 arith = -1.
37 let d3: i64 = __simd_vsra_i16_x16(a as *i64, 1, o as *i64)
38 let r3: i64 = __simd_vreduce_max_i16_x16(o as *i64)
39 if r3 != -1 { return 3 }
40 let r3b: i64 = __simd_vreduce_min_i16_x16(o as *i64)
41 if r3b != -1 { return 13 }
42
43 // Test 4: shift amount = 0 (identity).
44 a[0] = 0x0004000300020001
45 a[1] = 0x0008000700060005
46 a[2] = 0x000c000b000a0009
47 a[3] = 0x0010000f000e000d
48 let d4: i64 = __simd_vsll_i16_x16(a as *i64, 0, o as *i64)
49 let r4: i64 = __simd_vreduce_max_i16_x16(o as *i64)
50 if r4 != 16 { return 4 }
51 let r4b: i64 = __simd_vreduce_min_i16_x16(o as *i64)
52 if r4b != 1 { return 14 }
53
54 return 0
55}