code wiki / _hdl_build / nx_beat_wiring_register.nx
`nx_beat_wiring_register.nx` source

1// nx_beat_wiring_register.nx -- records R1-T1-003 + X-Q-007 (slow-beat
2// wiring as data + the seeded catch proof) and the lane-rc6 measurement
3// campaign.  Engineer gate = ATGATE 4/4 + DSEEDGATE 4/4 re-run GREEN at
4// register time.  Librarian alloc + dual-write.  license_tier: ORIGINAL
5import "nx_cap_register.nx"
6import "nx_capreg_librarian.nx"
7import "nx_syscalls.nx"
8
9func bwr_run(path: *u8) -> i64 {
10    let pid: i64 = sys_fork()
11    if pid == 0 {
12        let dn: i64 = sys_openat_wr("/dev/null" as *u8, 0x1a4)
13        if dn >= 0 { sys_dup3(dn, 1, 0); sys_dup3(dn, 2, 0) }
14        let argv: *i64 = sys_mmap(32) as *i64; argv[0] = path as i64; argv[1] = 0
15        let envp: *i64 = sys_mmap(16) as *i64; envp[0] = 0
16        sys_execve(path, argv, envp); sys_exit(127)
17    }
18    let st: *i64 = sys_mmap(16) as *i64
19    sys_wait4(pid, st, 0)
20    return st[0]
21}
22
23func main() -> i64 {
24    var allok: i64 = 1
25    if bwr_run("/tmp/_autorun_targets_gate_authored.sov.elf" as *u8) != 0 { allok = 0 }
26    if bwr_run("/tmp/_diff_seed_gate_authored.sov.elf" as *u8) != 0 { allok = 0 }
27    cr_w(1, "ENGINEER: ATGATE+DSEEDGATE re-run all-pass=" as *u8); cr_wn(1, allok); cr_w(1, "\n" as *u8)
28    let eng: i64 = ig_engineer(1, 1, 1, allok)
29    let dec: i64 = ig_decision(eng, ig_council(eng, 1, 1, 2), 1)
30    if dec != IG_INGEST { cr_w(1, "HELD\n" as *u8); sys_exit(1) }
31    if cr_can_register(5, 2, 6, dec) != 1 { cr_w(1, "REFUSED\n" as *u8); sys_exit(1) }
32    let lp: *u8 = "/tmp/nishi_cap_registry.log" as *u8
33    let jp: *u8 = "knowledge/status/cap_registry_durable.log" as *u8
34    let idx: i64 = cl_next_idx(lp, jp)
35    let ok: i64 = cl_register_dual(lp, jp, idx, 5,
36        2, "SELF SLOW-BEAT-AS-DATA + SEEDED-CATCH (R1-T1-003 + X-Q-007, both closed by reconcile) -- nx_ad_core/nx_autorun_daemon: the 6h beat's target list is CONF DATA (T <basename> rows in autorun_daemon.conf, re-read EVERY beat = edits apply без re-arm; no rows = historical math default; charset-validated boundary), per-target AUTORUN-TGT rows + BEAT row keeps rung_rc= for old readers; conf now runs math + nx_diff_cmp + _attempt_loop_gate (the diff harness and the attempt-loop gate re-prove on the slow beat). ATGATE 4/4 (parse/default-without-executing/charset-reject/real-lane toy beat worst-rc-law). Seeded catch: _dgseed900 fixture (4-deep ifs, hand-computed exit=1) -- bash-context lanes DIVERGE (sov=1 correct, KG=0 wrong) but CONTROLLED same-parent context AGREE; DSEEDGATE 4/4 mode=controlled-agree-context-artifact-said (no silent substitution; the divergence stands in R1-T1-006). MEASUREMENT CAMPAIGN (R1-T1-004 updated with strongest evidence yet): lane-parent nxasm rc=6 on nx_autorun_daemon 100pct-x6 while EVERY manual variant passes on md5-IDENTICAL .s (argv0 form, env rows, output path, sovereign-probe parent each ruled out SINGLY) = parent-context class in the toolchain, repro ON DEMAND via lane-build = the bisect fodder. Daemon staged manually (/tmp + DURABLE _offc/nx_autorun_daemon.elf, new artifact); live pid kept running; conf targets activate next re-arm. NOTE: revive-after-wipe depends on lane rebuild of THIS module = currently rc=6 -> the durable elf is the bridge, wire boot_revive fallback when T1-004 closes" as *u8)
37    if ok != 1 { cr_w(1, "DUAL-WRITE FAILED\n" as *u8); sys_exit(1) }
38    cr_w(1, "CAPREG idx=" as *u8); cr_wn(1, idx); cr_w(1, " REGISTERED -- the slow beat is data and the harness has teeth\n" as *u8)
39    sys_exit(0)
40    return 0
41}
nx_beat_wiring_register.nx source

`nx_beat_wiring_register.nx` source
