code wiki / _hdl_build / nx_clock_gate.nx
`nx_clock_gate.nx` source

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1// nx_clock_gate.nx -- proves the ONE Nishi clock (operator: "s class exceed like how pulses work on clocks ...
2// dont have a million pulses and daemons"). THE key property = the DIVIDER: a single tick source drives N jobs,
3// each at its own interval -- so j(1) fires every tick, j(2) every other, j(3) every third, all from ONE dispatcher
4// loop, never N pulse loops. Plus: re-register is idempotent (no duplicate pulse), a skipped tick can't cause a
5// runaway (catch-up safe), and the registry (name, interval, next_due, organ) is durable. license_tier: ORIGINAL  expect_exit: 0
6import "nx_clock_sched.nx"
7import "nx_syscalls.nx"
8import "nx_gate_verdict.nx"
9
10func w(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
11func wn(v: i64) -> i64 { var m: i64=v; if m<0{w("-" as *u8);m=0-m} let t:*u8=sys_mmap(24); var k:i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i:i64=0; let o:*u8=sys_mmap(24); while i<k{o[i]=t[k-1-i];i=i+1} sys_write(1,o,k); return 0 }
12func dun(p: *u8) -> i64 { __syscall(87, p as i64, 0, 0, 0, 0, 0); return 0 }
13
14func main(argc: i64, argv: *i64) -> i64 {
  w("=== nx_clock_gate -- ONE clock + a registry of interval-divided jobs (no pulse sprawl) ===\n" as *u8)
  let names: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW)
  let orgs: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW)
  let iv: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64
  let nd: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64
  let fired: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64
  let tally: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64
  let np: *i64 = sys_mmap(8) as *i64; np[0]=0
  // FIXTURE PATH IS SCRATCH, NEVER PRODUCTION (2026-08-03): this gate used to unlink AND rewrite
  // knowledge/sched/jobs.tsv -- the real (now retired, debt 1785792856) registry -- so every gate
  // run resurrected a retired production file with test rows in it. A test that writes where
  // production reads is a clobber wearing a lab coat.
  let freg: *u8 = "_build/_clkgate_reg.tsv" as *u8
  dun(freg)
  var pass: i64=0; var tot: i64=0
30
  // T1 DIVIDER: 3 jobs (intervals 1,2,3); advance the ONE clock ticks 1..6; tally fires per job.
  clk_register(names, orgs, iv, nd, np, "publisher_drain" as *u8, "_offc/nx_pub_ship_now.elf" as *u8, 1)
  clk_register(names, orgs, iv, nd, np, "research_cycle" as *u8, "_offc/nx_research_cycle.elf" as *u8, 2)
  clk_register(names, orgs, iv, nd, np, "selfscaffold_beat" as *u8, "_offc/ss_cycle_organ.elf" as *u8, 3)
  var i: i64=0; while i<np[0] { tally[i]=0; i=i+1 }
  var now: i64=1
  while now <= 6 {
      clk_tick(iv, nd, np[0], now, fired)
      var k: i64=0; while k<np[0] { if fired[k]==1 { tally[k]=tally[k]+1 } k=k+1 }
      now = now + 1
  }
  w("  over 6 ticks: j1(int1) fired="); wn(tally[0]); w(" j2(int2) fired="); wn(tally[1]); w(" j3(int3) fired="); wn(tally[2]); w("\n" as *u8)
  tot=tot+1; if tally[0]==6 { if tally[1]==3 { if tally[2]==2 { pass=pass+1; w("  PASS divider behavior exact (6/3/2 from ONE tick source)\n" as *u8) } else { w("  FAIL j3\n" as *u8) } } else { w("  FAIL j2\n" as *u8) } } else { w("  FAIL j1\n" as *u8) }
44
  // T2 IDEMPOTENT register: declaring the same job again must NOT add a second pulse
  let before: i64 = np[0]
  let added: i64 = clk_register(names, orgs, iv, nd, np, "publisher_drain" as *u8, "_offc/nx_pub_ship_now.elf" as *u8, 1)
  tot=tot+1; if added==0 { if np[0]==before { pass=pass+1; w("  PASS re-register is a no-op (no duplicate pulse)\n" as *u8) } else { w("  FAIL count grew\n" as *u8) } } else { w("  FAIL re-register added a job\n" as *u8) }
49
  // T3 CATCH-UP safe: a job (int 2) when the clock JUMPS to now=5 fires ONCE, then not again at the same now
  np[0]=0
  clk_register(names, orgs, iv, nd, np, "jslow" as *u8, "x" as *u8, 2)
  let c1: i64 = clk_tick(iv, nd, np[0], 5, fired)
  let c2: i64 = clk_tick(iv, nd, np[0], 5, fired)
  tot=tot+1; if c1==1 { if c2==0 { pass=pass+1; w("  PASS catch-up safe: skipped ticks -> fires ONCE, no runaway\n" as *u8) } else { w("  FAIL fired twice on same tick\n" as *u8) } } else { w("  FAIL did not fire on jump\n" as *u8) }
56
  // T4 DURABLE legacy registry (incl the organ path): save -> load -> identical jobs. The FILE codec
  // stays gated because it is the MIGRATION SOURCE (clk_load_state falls back to it exactly once).
  np[0]=0
  clk_register(names, orgs, iv, nd, np, "alpha" as *u8, "_offc/a.elf" as *u8, 4)
  clk_register(names, orgs, iv, nd, np, "beta" as *u8, "_offc/b.elf" as *u8, 7)
  clk_save(freg, names, orgs, iv, nd, np[0])
  let names2: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW); let orgs2: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW)
  let iv2: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64; let nd2: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64; let np2: *i64 = sys_mmap(8) as *i64
  clk_load(freg, names2, orgs2, iv2, nd2, np2)
  w("  reloaded jobs="); wn(np2[0]); w(" intervals="); wn(iv2[0]); w(","); wn(iv2[1]); w(" organ0="); w(clk_slot(orgs2,0)); w("\n" as *u8)
  tot=tot+1; if np2[0]==2 { if iv2[0]==4 { if iv2[1]==7 { if clk_streq(clk_slot(orgs2,0), "_offc/a.elf" as *u8)==1 { pass=pass+1; w("  PASS registry durable incl organ path (save->load identical)\n" as *u8) } else { w("  FAIL organ path lost\n" as *u8) } } else { w("  FAIL iv1\n" as *u8) } } else { w("  FAIL iv0\n" as *u8) } } else { w("  FAIL count\n" as *u8) }
68
  // T5 PLANE round-trip incl the WIDTH TOOTH (2026-08-03, debts 1784828927+1784413227): the state
  // SSOT is now a seg-store plane, and the organ slot must carry a 63-char _build abs path
  // UN-TRUNCATED -- the exact string shape that silently fork-failed 127 under CLK_NAMEW=48
  // (worldgen-gate/bootstrap-gate rows). A pass here kills the truncation mutant at its site.
  let longp: *u8 = "/volume1/homes/elderwesto/nishihost/buildroot/_build/nx_worldgen_gate.sov.elf" as *u8
  let tpfx: *u8 = "knowledge/store/clkgatetest-" as *u8
  np[0]=0
  clk_register(names, orgs, iv, nd, np, "gamma" as *u8, longp, 5)
  clk_register(names, orgs, iv, nd, np, "delta" as *u8, "nx_netobs.elf" as *u8, 9)
  nd[0] = 12345
  clk_save_plane(tpfx, names, orgs, iv, nd, np[0])
  let names3: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW); let orgs3: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW)
  let iv3: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64; let nd3: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64; let np3: *i64 = sys_mmap(8) as *i64
  clk_load_plane(tpfx, names3, orgs3, iv3, nd3, np3)
  w("  plane reloaded jobs="); wn(np3[0]); w(" nd0="); wn(nd3[0]); w(" organ0="); w(clk_slot(orgs3,0)); w("\n" as *u8)
  tot=tot+1; if np3[0]==2 { if nd3[0]==12345 { if clk_streq(clk_slot(orgs3,0), longp)==1 { pass=pass+1; w("  PASS plane state durable, 78-char organ path BYTE-EXACT (truncation class dead)\n" as *u8) } else { w("  FAIL long organ path truncated/lost\n" as *u8) } } else { w("  FAIL next_due lost\n" as *u8) } } else { w("  FAIL plane count\n" as *u8) }
85
  // T6 MIGRATION ORDER: an empty plane + a legacy file -> clk_load_state returns 1 (migrated) with
  // the legacy rows; after a plane save, the SAME call returns 0 (plane wins). Both polarities in
  // one tooth: the fallback fires exactly when the plane is empty and never after.
  let mpfx: *u8 = "knowledge/store/clkgatemig-" as *u8
  let e0: *u8 = sys_mmap(8); e0[0] = 0 as u8
  // force the test plane EMPTY with a RAW zero-byte seed -- clk_save_plane would reload-merge a
  // previous gate run's rows back in (that merge is the production feature; here it must be bypassed)
  sts_seed(mpfx, e0, 0)
  let np4: *i64 = sys_mmap(8) as *i64
  let src1: i64 = clk_load_state(mpfx, freg, names2, orgs2, iv2, nd2, np4)
  let mig_rows: i64 = np4[0]
  clk_save_plane(mpfx, names2, orgs2, iv2, nd2, np4[0])
  let src2: i64 = clk_load_state(mpfx, freg, names3, orgs3, iv3, nd3, np4)
  w("  migration: first load src="); wn(src1); w(" rows="); wn(mig_rows); w("  after plane-save src="); wn(src2); w("\n" as *u8)
  tot=tot+1; if src1==1 { if mig_rows==2 { if src2==0 { pass=pass+1; w("  PASS one-time migration: legacy fires ONLY on an empty plane, plane wins thereafter\n" as *u8) } else { w("  FAIL plane did not win after save\n" as *u8) } } else { w("  FAIL legacy rows not loaded\n" as *u8) } } else { w("  FAIL fallback did not fire\n" as *u8) }
101
  w("nx_clock_gate pass="); wn(pass); w("/"); wn(tot)
  // MIGRATED onto nx_gate_verdict by nx_gate_dry_apply (D001, minimal form): every check
  // row above is untouched, so the PASS/FAIL vector cannot change; only the hand-rolled
  // verdict emission is replaced by the ONE shared base class. Proven by nx_gate_migrate verify.
  let ctr__dry: *i64 = gv_ctr()
  ctr__dry[0] = pass
  ctr__dry[1] = tot
  let rc__dry: i64 = gv_verdict("CLOCK-GATE" as *u8, ctr__dry, "ONE clock + plane-SSOT registry of dividers = every pulse derived from one source, no sprawl, no tsv)" as *u8)
  sys_exit(rc__dry)
  return rc__dry
112}
nx_clock_gate.nx source

`nx_clock_gate.nx` source
