nx_clock_gate.nx source

1// nx_clock_gate.nx -- proves the ONE Nishi clock (operator: "s class exceed like how pulses work on clocks ... 2// dont have a million pulses and daemons"). THE key property = the DIVIDER: a single tick source drives N jobs, 3// each at its own interval -- so j(1) fires every tick, j(2) every other, j(3) every third, all from ONE dispatcher 4// loop, never N pulse loops. Plus: re-register is idempotent (no duplicate pulse), a skipped tick can't cause a 5// runaway (catch-up safe), and the registry (name, interval, next_due, organ) is durable. license_tier: ORIGINAL expect_exit: 0 6import "nx_clock_sched.nx" 7import "nx_syscalls.nx" 8 9func w(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } 10func wn(v: i64) -> i64 { var m: i64=v; if m<0{w("-" as *u8);m=0-m} let t:*u8=sys_mmap(24); var k:i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i:i64=0; let o:*u8=sys_mmap(24); while i<k{o[i]=t[k-1-i];i=i+1} sys_write(1,o,k); return 0 } 11func dun(p: *u8) -> i64 { __syscall(87, p as i64, 0, 0, 0, 0, 0); return 0 } 12 13func main(argc: i64, argv: *i64) -> i64 { 14 w("=== nx_clock_gate -- ONE clock + a registry of interval-divided jobs (no pulse sprawl) ===\n" as *u8) 15 let names: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW) 16 let orgs: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW) 17 let iv: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64 18 let nd: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64 19 let fired: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64 20 let tally: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64 21 let np: *i64 = sys_mmap(8) as *i64; np[0]=0 22 // FIXTURE PATH IS SCRATCH, NEVER PRODUCTION (2026-08-03): this gate used to unlink AND rewrite 23 // knowledge/sched/jobs.tsv -- the real (now retired, debt 1785792856) registry -- so every gate 24 // run resurrected a retired production file with test rows in it. A test that writes where 25 // production reads is a clobber wearing a lab coat. 26 let freg: *u8 = "_build/_clkgate_reg.tsv" as *u8 27 dun(freg) 28 var pass: i64=0; var tot: i64=0 29 30 // T1 DIVIDER: 3 jobs (intervals 1,2,3); advance the ONE clock ticks 1..6; tally fires per job. 31 clk_register(names, orgs, iv, nd, np, "publisher_drain" as *u8, "_offc/nx_pub_ship_now.elf" as *u8, 1) 32 clk_register(names, orgs, iv, nd, np, "research_cycle" as *u8, "_offc/nx_research_cycle.elf" as *u8, 2) 33 clk_register(names, orgs, iv, nd, np, "selfscaffold_beat" as *u8, "_offc/ss_cycle_organ.elf" as *u8, 3) 34 var i: i64=0; while i<np[0] { tally[i]=0; i=i+1 } 35 var now: i64=1 36 while now <= 6 { 37 clk_tick(iv, nd, np[0], now, fired) 38 var k: i64=0; while k<np[0] { if fired[k]==1 { tally[k]=tally[k]+1 } k=k+1 } 39 now = now + 1 40 } 41 w(" over 6 ticks: j1(int1) fired="); wn(tally[0]); w(" j2(int2) fired="); wn(tally[1]); w(" j3(int3) fired="); wn(tally[2]); w("\n" as *u8) 42 tot=tot+1; if tally[0]==6 { if tally[1]==3 { if tally[2]==2 { pass=pass+1; w(" PASS divider behavior exact (6/3/2 from ONE tick source)\n" as *u8) } else { w(" FAIL j3\n" as *u8) } } else { w(" FAIL j2\n" as *u8) } } else { w(" FAIL j1\n" as *u8) } 43 44 // T2 IDEMPOTENT register: declaring the same job again must NOT add a second pulse 45 let before: i64 = np[0] 46 let added: i64 = clk_register(names, orgs, iv, nd, np, "publisher_drain" as *u8, "_offc/nx_pub_ship_now.elf" as *u8, 1) 47 tot=tot+1; if added==0 { if np[0]==before { pass=pass+1; w(" PASS re-register is a no-op (no duplicate pulse)\n" as *u8) } else { w(" FAIL count grew\n" as *u8) } } else { w(" FAIL re-register added a job\n" as *u8) } 48 49 // T3 CATCH-UP safe: a job (int 2) when the clock JUMPS to now=5 fires ONCE, then not again at the same now 50 np[0]=0 51 clk_register(names, orgs, iv, nd, np, "jslow" as *u8, "x" as *u8, 2) 52 let c1: i64 = clk_tick(iv, nd, np[0], 5, fired) 53 let c2: i64 = clk_tick(iv, nd, np[0], 5, fired) 54 tot=tot+1; if c1==1 { if c2==0 { pass=pass+1; w(" PASS catch-up safe: skipped ticks -> fires ONCE, no runaway\n" as *u8) } else { w(" FAIL fired twice on same tick\n" as *u8) } } else { w(" FAIL did not fire on jump\n" as *u8) } 55 56 // T4 DURABLE legacy registry (incl the organ path): save -> load -> identical jobs. The FILE codec 57 // stays gated because it is the MIGRATION SOURCE (clk_load_state falls back to it exactly once). 58 np[0]=0 59 clk_register(names, orgs, iv, nd, np, "alpha" as *u8, "_offc/a.elf" as *u8, 4) 60 clk_register(names, orgs, iv, nd, np, "beta" as *u8, "_offc/b.elf" as *u8, 7) 61 clk_save(freg, names, orgs, iv, nd, np[0]) 62 let names2: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW); let orgs2: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW) 63 let iv2: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64; let nd2: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64; let np2: *i64 = sys_mmap(8) as *i64 64 clk_load(freg, names2, orgs2, iv2, nd2, np2) 65 w(" reloaded jobs="); wn(np2[0]); w(" intervals="); wn(iv2[0]); w(","); wn(iv2[1]); w(" organ0="); w(clk_slot(orgs2,0)); w("\n" as *u8) 66 tot=tot+1; if np2[0]==2 { if iv2[0]==4 { if iv2[1]==7 { if clk_streq(clk_slot(orgs2,0), "_offc/a.elf" as *u8)==1 { pass=pass+1; w(" PASS registry durable incl organ path (save->load identical)\n" as *u8) } else { w(" FAIL organ path lost\n" as *u8) } } else { w(" FAIL iv1\n" as *u8) } } else { w(" FAIL iv0\n" as *u8) } } else { w(" FAIL count\n" as *u8) } 67 68 // T5 PLANE round-trip incl the WIDTH TOOTH (2026-08-03, debts 1784828927+1784413227): the state 69 // SSOT is now a seg-store plane, and the organ slot must carry a 63-char _build abs path 70 // UN-TRUNCATED -- the exact string shape that silently fork-failed 127 under CLK_NAMEW=48 71 // (worldgen-gate/bootstrap-gate rows). A pass here kills the truncation mutant at its site. 72 let longp: *u8 = "/volume1/homes/elderwesto/nishihost/buildroot/_build/nx_worldgen_gate.sov.elf" as *u8 73 let tpfx: *u8 = "knowledge/store/clkgatetest-" as *u8 74 np[0]=0 75 clk_register(names, orgs, iv, nd, np, "gamma" as *u8, longp, 5) 76 clk_register(names, orgs, iv, nd, np, "delta" as *u8, "nx_netobs.elf" as *u8, 9) 77 nd[0] = 12345 78 clk_save_plane(tpfx, names, orgs, iv, nd, np[0]) 79 let names3: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW); let orgs3: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW) 80 let iv3: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64; let nd3: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64; let np3: *i64 = sys_mmap(8) as *i64 81 clk_load_plane(tpfx, names3, orgs3, iv3, nd3, np3) 82 w(" plane reloaded jobs="); wn(np3[0]); w(" nd0="); wn(nd3[0]); w(" organ0="); w(clk_slot(orgs3,0)); w("\n" as *u8) 83 tot=tot+1; if np3[0]==2 { if nd3[0]==12345 { if clk_streq(clk_slot(orgs3,0), longp)==1 { pass=pass+1; w(" PASS plane state durable, 78-char organ path BYTE-EXACT (truncation class dead)\n" as *u8) } else { w(" FAIL long organ path truncated/lost\n" as *u8) } } else { w(" FAIL next_due lost\n" as *u8) } } else { w(" FAIL plane count\n" as *u8) } 84 85 // T6 MIGRATION ORDER: an empty plane + a legacy file -> clk_load_state returns 1 (migrated) with 86 // the legacy rows; after a plane save, the SAME call returns 0 (plane wins). Both polarities in 87 // one tooth: the fallback fires exactly when the plane is empty and never after. 88 let mpfx: *u8 = "knowledge/store/clkgatemig-" as *u8 89 let e0: *u8 = sys_mmap(8); e0[0] = 0 as u8 90 // force the test plane EMPTY with a RAW zero-byte seed -- clk_save_plane would reload-merge a 91 // previous gate run's rows back in (that merge is the production feature; here it must be bypassed) 92 sts_seed(mpfx, e0, 0) 93 let np4: *i64 = sys_mmap(8) as *i64 94 let src1: i64 = clk_load_state(mpfx, freg, names2, orgs2, iv2, nd2, np4) 95 let mig_rows: i64 = np4[0] 96 clk_save_plane(mpfx, names2, orgs2, iv2, nd2, np4[0]) 97 let src2: i64 = clk_load_state(mpfx, freg, names3, orgs3, iv3, nd3, np4) 98 w(" migration: first load src="); wn(src1); w(" rows="); wn(mig_rows); w(" after plane-save src="); wn(src2); w("\n" as *u8) 99 tot=tot+1; if src1==1 { if mig_rows==2 { if src2==0 { pass=pass+1; w(" PASS one-time migration: legacy fires ONLY on an empty plane, plane wins thereafter\n" as *u8) } else { w(" FAIL plane did not win after save\n" as *u8) } } else { w(" FAIL legacy rows not loaded\n" as *u8) } } else { w(" FAIL fallback did not fire\n" as *u8) } 100 101 w("nx_clock_gate pass="); wn(pass); w("/"); wn(tot) 102 if pass==tot { w(" verdict=GREEN (ONE clock + plane-SSOT registry of dividers = every pulse derived from one source, no sprawl, no tsv)\n" as *u8); sys_exit(0); return 0 } 103 w(" verdict=RED\n" as *u8); sys_exit(1); return 1 104}