code wiki / _hdl_build / nx_clock_tickless_gate.nx
`nx_clock_tickless_gate.nx` source

1// nx_clock_tickless_gate.nx -- proves the TICKLESS driver (sched_tickless.raw lesson) entirely IN the nishi
2// ecosystem (a harness-run gate, no shell hand-driving). Two sparse jobs (intervals 3 and 5, no interval-1) are
3// registered via clk_register; the tickless loop wakes ONLY at the minimum next_due, skipping every idle tick. It
4// reaches tick 12 in just 6 wakes (skipping 6 idle ticks), and each wake fork+execs the real blessed marker organ
5// (_offc/nx_clock_marker.elf) which increments a counter -> proven REAL execution, not a constant tick.
6// license_tier: ORIGINAL  expect_exit: 0
7import "nx_clock_sched.nx"
8import "nx_syscalls.nx"
9import "nx_gate_verdict.nx"
10
11const TLG_MAXBEATS: i64 = 6
12const TLG_TICK_MS:  i64 = 20
13
14func w(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
15func wn(v: i64) -> i64 { var m: i64=v; if m<0{w("-" as *u8);m=0-m} let t:*u8=sys_mmap(24); var k:i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i:i64=0; let o:*u8=sys_mmap(24); while i<k{o[i]=t[k-1-i];i=i+1} sys_write(1,o,k); return 0 }
16func dun(p: *u8) -> i64 { __syscall(87, p as i64, 0, 0, 0, 0, 0); return 0 }
17func readnum(p: *u8) -> i64 { let lp: *i64 = sys_mmap(8) as *i64; let d: *u8 = sys_read_file(p, lp); if (d as i64)==0 { return 0 } var c: i64=0; var i: i64=0; while i<lp[0] { if d[i]>=(48 as u8) { if d[i]<=(57 as u8) { c=c*10+(d[i]-(48 as u8)) as i64 } } i=i+1 } return c }
18
19func main(argc: i64, argv: *i64) -> i64 {
20    w("=== nx_clock_tickless_gate -- wake only when due, skip idle ticks (no shell) ===\n" as *u8)
21    let names: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW); let orgs: *u8 = sys_mmap(CLK_MAXJOBS*CLK_NAMEW)
22    let iv: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64; let nd: *i64 = sys_mmap(CLK_MAXJOBS*8) as *i64
23    let np: *i64 = sys_mmap(8) as *i64; np[0]=0
24    clk_register(names, orgs, iv, nd, np, "mj3" as *u8, "_offc/nx_clock_marker.elf" as *u8, 3)
25    clk_register(names, orgs, iv, nd, np, "mj5" as *u8, "_offc/nx_clock_marker.elf" as *u8, 5)
26    dun("/tmp/clk_mark.txt" as *u8)   // reset the marker counter (sovereign unlink, not `rm`)
27
28    let out: *i64 = sys_mmap(64) as *i64
29    clk_run_tickless(orgs, iv, nd, np[0], 0, TLG_MAXBEATS, TLG_TICK_MS, out)   // the PRODUCTION tickless loop, under test
30    let beats: i64 = out[0]; let dispatches: i64 = out[1]; let skipped: i64 = out[2]; let T: i64 = out[3]
31    let ran: i64 = readnum("/tmp/clk_mark.txt" as *u8)
32    w("  reached tick " as *u8); wn(T); w(" in " as *u8); wn(beats); w(" wakes; SKIPPED " as *u8); wn(skipped); w(" idle ticks; organ ran " as *u8); wn(ran); w(" times\n" as *u8)
33
34    var pass: i64=0; var tot: i64=0
35    // T1 TICKLESS: reached a far tick in fewer wakes than ticks elapsed (skipped idle ticks)
36    tot=tot+1; if skipped > 0 { if beats < T { pass=pass+1; w("  PASS tickless: tick " as *u8); wn(T); w(" in only " as *u8); wn(beats); w(" wakes (no constant tick)\n" as *u8) } else { w("  FAIL woke every tick\n" as *u8) } } else { w("  FAIL skipped 0 idle ticks\n" as *u8) }
37    // T2 REAL execution: the blessed marker organ ran once per dispatch
38    tot=tot+1; if ran == dispatches { if ran > 0 { pass=pass+1; w("  PASS organ ran " as *u8); wn(ran); w("x = every dispatch really executed\n" as *u8) } else { w("  FAIL organ never ran\n" as *u8) } } else { w("  FAIL ran(" as *u8); wn(ran); w(")!=dispatches(" as *u8); wn(dispatches); w(")\n" as *u8) }
39    // T3 EXACT divider schedule: ticks 3,5,6,9,10,12 -> 6 beats, 6 dispatch, 6 skipped, final 12
40    tot=tot+1; if beats==6 { if dispatches==6 { if skipped==6 { if T==12 { pass=pass+1; w("  PASS exact: 6 wakes / 6 dispatch / 6 skipped / tick 12\n" as *u8) } else { w("  FAIL tick!=12\n" as *u8) } } else { w("  FAIL skipped!=6\n" as *u8) } } else { w("  FAIL dispatch!=6\n" as *u8) } } else { w("  FAIL beats!=6\n" as *u8) }
41
42    w("nx_clock_tickless_gate pass=" as *u8); wn(pass); w("/" as *u8); wn(tot)
43    // MIGRATED onto nx_gate_verdict by nx_gate_dry_apply (D001, minimal form): every check
44    // row above is untouched, so the PASS/FAIL vector cannot change; only the hand-rolled
45    // verdict emission is replaced by the ONE shared base class. Proven by nx_gate_migrate verify.
46    let ctr__dry: *i64 = gv_ctr()
47    ctr__dry[0] = pass
48    ctr__dry[1] = tot
49    let rc__dry: i64 = gv_verdict("CLOCK-TICKLESS-GATE" as *u8, ctr__dry, "tickless: one spark, sparse wakes, real organ execution)" as *u8)
50    sys_exit(rc__dry)
51    return rc__dry
52}
nx_clock_tickless_gate.nx source

`nx_clock_tickless_gate.nx` source
