nx_depcycle_gate.nx source

1// nx_depcycle_gate.nx -- GATE for the Acyclic Dependencies checker (5 teeth incl neg-controls + 2// determinism + MUTATION). PREREQ: stage _offc/nx_depcycle.elf. Run from nxc2 root. One fork/tooth. 3// T1 ACYCLIC (a->b->c) | T2 CYCLIC-2 (a<->b) names both CYCLENODEs | T3 3-cycle CYCLIC-3 | T4 4// determinism | T5 MUTATION break the 2-cycle -> ACYCLIC (the detector genuinely tracks the edge). 5// license_tier: ORIGINAL No hw writes (Rule 26). 6import "nx_seat_drive_lib.nx" 7import "nx_seg_store.nx" 8import "nx_deploy_lib.nx" 9import "nx_syscalls.nx" 10 11func dg_atoi(s: *u8) -> i64 { var v: i64 = 0; var i: i64 = 0; while s[i] != (0 as u8) { let c: i64 = s[i] as i64; if c >= 48 { if c <= 57 { v = v * 10 + (c - 48) } } i = i + 1 } return v } 12func dg_itoa(dst: *u8, v: i64) -> i64 { var m: i64 = v; let t: *u8 = sys_mmap(24); var k: i64 = 0; if m == 0 { t[0] = 48 as u8; k = 1 } while m > 0 { t[k] = (48 + (m % 10)) as u8; m = m / 10; k = k + 1 } var i: i64 = 0; while i < k { dst[i] = t[k - 1 - i]; i = i + 1 } dst[k] = 0 as u8; return k } 13func dg_len(s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } return n } 14 15func dg_run(dir: *u8, outp: *u8) -> i64 { 16 let av: *i64 = sys_mmap(16) as *i64 17 av[0] = dir as i64 18 return dep_run_capture("_offc/nx_depcycle.elf" as *u8, av, 1, outp) 19} 20 21func main(argc: i64, argv: *i64) -> i64 { 22 var stage: i64 = 1 23 var pass: i64 = 0 24 if argc >= 2 { let ss1: *u8 = argv[1] as *u8; stage = dg_atoi(ss1) } 25 if argc >= 3 { let ps: *u8 = argv[2] as *u8; pass = dg_atoi(ps) } 26 if stage < 1 { stage = 1 } 27 28 // acyclic dir 29 sys_mkdir("/tmp/dcac" as *u8, 0x1ed) 30 let aca: *u8 = "import \"b.nx\"\nfunc a() -> i64 { return 1 }\n" as *u8 31 ss_writefile("/tmp/dcac/a.nx" as *u8, aca, dg_len(aca)) 32 let acb: *u8 = "import \"c.nx\"\nfunc b() -> i64 { return 2 }\n" as *u8 33 ss_writefile("/tmp/dcac/b.nx" as *u8, acb, dg_len(acb)) 34 let acc: *u8 = "func c() -> i64 { return 3 }\n" as *u8 35 ss_writefile("/tmp/dcac/c.nx" as *u8, acc, dg_len(acc)) 36 // 2-cycle dir 37 sys_mkdir("/tmp/dccyc" as *u8, 0x1ed) 38 let cya: *u8 = "import \"b.nx\"\nfunc a() -> i64 { return 1 }\n" as *u8 39 ss_writefile("/tmp/dccyc/a.nx" as *u8, cya, dg_len(cya)) 40 let cyb: *u8 = "import \"a.nx\"\nfunc b() -> i64 { return 2 }\n" as *u8 41 ss_writefile("/tmp/dccyc/b.nx" as *u8, cyb, dg_len(cyb)) 42 43 if stage == 1 { 44 let rc: i64 = dg_run("/tmp/dcac" as *u8, "/tmp/dc_t1.out" as *u8) 45 let out: *u8 = sys_mmap(16384) 46 let n: i64 = dp_read("/tmp/dc_t1.out" as *u8, out, 16384) 47 var ok: i64 = 0 48 if rc == 0 { if sd_count(out, n, "verdict=ACYCLIC\n" as *u8) == 1 { if sd_count(out, n, "edges=2 " as *u8) == 1 { ok = 1 } } } 49 if ok == 1 { sd_w("T1 acyclic-chain PASS\n" as *u8); pass = pass + 1 } else { sd_w("T1 acyclic-chain FAIL\n" as *u8) } 50 } 51 if stage == 2 { 52 let rc: i64 = dg_run("/tmp/dccyc" as *u8, "/tmp/dc_t2.out" as *u8) 53 let out: *u8 = sys_mmap(16384) 54 let n: i64 = dp_read("/tmp/dc_t2.out" as *u8, out, 16384) 55 var ok: i64 = 0 56 if rc == 0 { if sd_count(out, n, "verdict=CYCLIC-2\n" as *u8) == 1 { if sd_count(out, n, "CYCLENODE a.nx" as *u8) == 1 { if sd_count(out, n, "CYCLENODE b.nx" as *u8) == 1 { ok = 1 } } } } 57 if ok == 1 { sd_w("T2 two-cycle-named PASS\n" as *u8); pass = pass + 1 } else { sd_w("T2 two-cycle-named FAIL\n" as *u8) } 58 } 59 if stage == 3 { 60 sys_mkdir("/tmp/dc3" as *u8, 0x1ed) 61 let a3: *u8 = "import \"b.nx\"\nfunc a() -> i64 { return 1 }\n" as *u8 62 ss_writefile("/tmp/dc3/a.nx" as *u8, a3, dg_len(a3)) 63 let b3: *u8 = "import \"c.nx\"\nfunc b() -> i64 { return 2 }\n" as *u8 64 ss_writefile("/tmp/dc3/b.nx" as *u8, b3, dg_len(b3)) 65 let c3: *u8 = "import \"a.nx\"\nfunc c() -> i64 { return 3 }\n" as *u8 66 ss_writefile("/tmp/dc3/c.nx" as *u8, c3, dg_len(c3)) 67 let rc: i64 = dg_run("/tmp/dc3" as *u8, "/tmp/dc_t3.out" as *u8) 68 let out: *u8 = sys_mmap(16384) 69 let n: i64 = dp_read("/tmp/dc_t3.out" as *u8, out, 16384) 70 var ok: i64 = 0 71 if rc == 0 { if sd_count(out, n, "verdict=CYCLIC-3\n" as *u8) == 1 { ok = 1 } } 72 if ok == 1 { sd_w("T3 three-cycle PASS\n" as *u8); pass = pass + 1 } else { sd_w("T3 three-cycle FAIL\n" as *u8) } 73 } 74 if stage == 4 { 75 let rc: i64 = dg_run("/tmp/dccyc" as *u8, "/tmp/dc_t4.out" as *u8) 76 let a: *u8 = sys_mmap(16384) 77 let an: i64 = dp_read("/tmp/dc_t2.out" as *u8, a, 16384) 78 let b: *u8 = sys_mmap(16384) 79 let bn: i64 = dp_read("/tmp/dc_t4.out" as *u8, b, 16384) 80 var same: i64 = 0 81 if rc == 0 { if an == bn { if an > 0 { same = 1; var i: i64 = 0; while i < an { if a[i] != b[i] { same = 0; i = an } else { i = i + 1 } } } } } 82 if same == 1 { sd_w("T4 deterministic PASS\n" as *u8); pass = pass + 1 } else { sd_w("T4 deterministic FAIL\n" as *u8) } 83 } 84 if stage == 5 { 85 // MUTATION: break the 2-cycle (b stops importing a) -> ACYCLIC 86 let mb: *u8 = "func b() -> i64 { return 2 }\n" as *u8 87 ss_writefile("/tmp/dccyc/b.nx" as *u8, mb, dg_len(mb)) 88 let rc: i64 = dg_run("/tmp/dccyc" as *u8, "/tmp/dc_t5.out" as *u8) 89 let out: *u8 = sys_mmap(16384) 90 let n: i64 = dp_read("/tmp/dc_t5.out" as *u8, out, 16384) 91 var ok: i64 = 0 92 if rc == 0 { if sd_count(out, n, "verdict=ACYCLIC\n" as *u8) == 1 { ok = 1 } } 93 if ok == 1 { sd_w("T5 mutation-break-cycle PASS\n" as *u8); pass = pass + 1 } else { sd_w("T5 mutation-break-cycle FAIL\n" as *u8) } 94 } 95 96 if stage >= 5 { 97 sd_w("NX-DEPCYCLE-GATE pass=" as *u8) 98 let pb: *u8 = sys_mmap(8) 99 pb[0] = (48 + pass) as u8 100 pb[1] = 0 as u8 101 sd_w(pb) 102 if pass == 5 { sd_w("/5 verdict=GREEN\n" as *u8); sys_exit(0); return 0 } 103 sd_w("/5 verdict=RED\n" as *u8) 104 sys_exit(1) 105 return 1 106 } 107 108 let self: *u8 = argv[0] as *u8 109 let sb: *u8 = sys_mmap(24) 110 dg_itoa(sb, stage + 1) 111 let pb2: *u8 = sys_mmap(24) 112 dg_itoa(pb2, pass) 113 let nav: *i64 = sys_mmap(40) as *i64 114 nav[0] = self as i64 115 nav[1] = sb as i64 116 nav[2] = pb2 as i64 117 nav[3] = 0 118 let envp: *i64 = sys_mmap(16) as *i64 119 envp[0] = 0 120 sys_execve(self, nav, envp) 121 sd_w("DCG-EXEC-FAIL\n" as *u8) 122 sys_exit(1) 123 return 1 124}