code wiki / _hdl_build / nx_dispatch_register.nx
`nx_dispatch_register.nx` source

1// nx_dispatch_register.nx -- registers the Conductor sequencer + queue via the
2// Librarian.  Evidence = the dispatch gate (scratch-queue KATs) + a live run
3// over the real queue, re-run here.
4// license_tier: ORIGINAL
5import "nx_cap_register.nx"
6import "nx_capreg_librarian.nx"
7import "nx_syscalls.nx"
8
9func dpr_run(path: *u8) -> i64 {
10    let pid: i64 = sys_fork()
11    if pid == 0 {
12        let dn: i64 = sys_openat_wr("/dev/null" as *u8, 0x1a4)
13        if dn >= 0 { sys_dup3(dn, 1, 0); sys_dup3(dn, 2, 0) }
14        let argv: *i64 = sys_mmap(32) as *i64; argv[0] = path as i64; argv[1] = 0
15        let envp: *i64 = sys_mmap(16) as *i64; envp[0] = 0
16        sys_execve(path, argv, envp); sys_exit(127)
17    }
18    let st: *i64 = sys_mmap(16) as *i64
19    sys_wait4(pid, st, 0)
20    return st[0]
21}
22
23func main() -> i64 {
24    var allok: i64 = 1
25    if dpr_run("/tmp/_assign_next_gate_authored.sov.elf" as *u8) != 0 { allok = 0 }
26    if dpr_run("/tmp/nx_assign_next.sov.elf" as *u8) != 0 { allok = 0 }
27    cr_w(1, "ENGINEER: dispatch gate + live queue run pass=" as *u8); cr_wn(1, allok); cr_w(1, "\n" as *u8)
28    let eng: i64 = ig_engineer(1, 1, 1, allok)
29    let dec: i64 = ig_decision(eng, ig_council(eng, 1, 1, 2), 1)
30    if dec != IG_INGEST { cr_w(1, "HELD\n" as *u8); sys_exit(1) }
31    if cr_can_register(5, 2, 6, dec) != 1 { cr_w(1, "REFUSED\n" as *u8); sys_exit(1) }
32    let lp: *u8 = "/tmp/nishi_cap_registry.log" as *u8
33    let jp: *u8 = "knowledge/status/cap_registry_durable.log" as *u8
34    let idx: i64 = cl_next_idx(lp, jp)
35    let ok: i64 = cl_register_dual(lp, jp, idx, 5,
36        2, "GEN S-CLASS-EXCEED PROGRAM QUEUE + CONDUCTOR SEQUENCER (RACI-clean orchestration, operator-corrected mid-build): the whole hardware-up program is now a MACHINE QUEUE the team works itself. (1) knowledge/registry/assignment_queue.tsv: ~1,240-assignment program (count model per rung in spec ADDENDUM), 100 seeded rows (enumerable ladders) + GEN markers (census-generated ~800), columns id/rung/w/size/owner/status/deps/gate; DONE flips only on gate markers. (2) nx_assign_core + nx_assign_next (CAPREG this): Conductor SEQUENCING verb ONLY -- priority w column is PM-OWNED (advisory seed; PM-RESCORE card routes it through the EXISTING nx_pm_decision_matrix WSJF -- duplication caught by operator and corrected: composes nx_pm_choose READY rule + nx_work_dispatcher, does not re-own CHOOSE); deps-DONE readiness gate; Auditor STRUCTVIEW (dep-graph largest blocker) with VIEWPOINT-DISCREPANCY when structure outranks the PM column; RAISEDHANDS = NOVEL tutor batch (the token-efficiency lever: tokens are spent ONLY on raised hands, batched). Gate GREEN first run (scratch-queue KATs: pick/dep-block/unblock/struct/novel). FIRST LIVE RUN judged itself: top pick = X-PM-001 (PM re-score = the team taking ownership of its own priorities) and STRUCTVIEW immediately caught a REAL advisory-weight error (X-S1d-001 blocks 6 rows, was weighted 7) = the discrepancy mechanism working on its author. Pulse step 20. LIVING-ROADMAP arc L + token-efficiency arc E filed as queue rows (L1 census-fetch via own-TLS+CAS, L2 distill, L3 evidence-derived roadmap render, L4 freshness drift gate, L5 bench-suite acquisition; E1 token-meter, E2 tutor-batching, E3 efficiency trend on the heartbeat). Composes CAPREG372/373/375" as *u8)
37    if ok != 1 { cr_w(1, "DUAL-WRITE FAILED\n" as *u8); sys_exit(1) }
38    cr_w(1, "CAPREG idx=" as *u8); cr_wn(1, idx); cr_w(1, " REGISTERED (program queue + Conductor sequencer)\n" as *u8)
39    sys_exit(0)
40    return 0
41}
nx_dispatch_register.nx source

`nx_dispatch_register.nx` source
