code wiki / _hdl_build / nx_f64_register.nx
`nx_f64_register.nx` source

1// nx_f64_register.nx -- registers the ME0 binary64 keystone through the Librarian's
2// repaired registry (cl_next_idx atomic allocation + cl_register_dual live+journal --
3// the cross-session collision + crash-survival fixes).  ENGINEER evidence = the
4// _f64_gate_authored KAT gate (1217 hardware-IEEE oracle vectors) re-run RIGHT HERE,
5// not asserted: the register refuses unless the gate exits 0 in this very process tree.
6// license_tier: ORIGINAL
7import "nx_cap_register.nx"
8import "nx_capreg_librarian.nx"
9import "nx_syscalls.nx"
10
11func f6r_run(path: *u8) -> i64 {
12    let pid: i64 = sys_fork()
13    if pid == 0 {
14        let dn: i64 = sys_openat_wr("/dev/null" as *u8, 0x1a4)
15        if dn >= 0 { sys_dup3(dn, 1, 0); sys_dup3(dn, 2, 0) }
16        let argv: *i64 = sys_mmap(32) as *i64; argv[0] = path as i64; argv[1] = 0
17        let envp: *i64 = sys_mmap(16) as *i64; envp[0] = 0
18        sys_execve(path, argv, envp); sys_exit(127)
19    }
20    let st: *i64 = sys_mmap(16) as *i64
21    sys_wait4(pid, st, 0)
22    return st[0]
23}
24
25func main() -> i64 {
26    var allok: i64 = 1
27    if f6r_run("/tmp/_f64_gate_authored.sov.elf" as *u8) != 0 { allok = 0 }
28    cr_w(1, "ENGINEER: f64 KAT gate (1217 hardware-IEEE vectors) pass=" as *u8); cr_wn(1, allok); cr_w(1, "\n" as *u8)
29    let eng: i64 = ig_engineer(1, 1, 1, allok)
30    let dec: i64 = ig_decision(eng, ig_council(eng, 1, 1, 2), 1)
31    if dec != IG_INGEST { cr_w(1, "HELD\n" as *u8); sys_exit(1) }
32    if cr_can_register(5, 2, 6, dec) != 1 { cr_w(1, "REFUSED\n" as *u8); sys_exit(1) }
33    let lp: *u8 = "/tmp/nishi_cap_registry.log" as *u8
34    let jp: *u8 = "knowledge/status/cap_registry_durable.log" as *u8
35    let idx: i64 = cl_next_idx(lp, jp)
36    let ok: i64 = cl_register_dual(lp, jp, idx, 5,
37        2, "GEN F64-BITS-UP (ME0 keystone, math-engine-exceed ladder rung 0) -- IEEE 754 binary64 FULLY bits-up on i64: nx_f64 (classify/neg/abs/eq/lt + add/sub correctly-rounded RNE w/ sticky-jam GRS) + nx_f64_div (restoring 56-bit quotient, EXACT guard both alignment cases) + nx_f64_sqrt (digit-pair restoring, 54-bit root) + nx_f64_cvt (i64->f64, f64->f32 narrowing). 106-bit significand product via 26/27 split (probe-verified partials). EXCEEDS f32 v1 family: subnormals pre-normalized, outputs denormalized BEFORE rounding = correctly rounded over the WHOLE domain incl. subnormal div (f32 v1 punts those). GATE: _f64_gate_authored 1217/1217 BIT-EXACT vs hardware-IEEE oracle (_f64_oracle_gen.py, edge cross-products + seeded randoms: subnormal/inf/NaN/ties/overflow), tamper-tested RED->GREEN. Unblocks L5 of numeric tower + ME1 transcendentals + DLMF special functions + f64-as-oracle for q4k/f16 VRAM-reduction grading" as *u8)
38    if ok != 1 { cr_w(1, "DUAL-WRITE FAILED\n" as *u8); sys_exit(1) }
39    cr_w(1, "CAPREG idx=" as *u8); cr_wn(1, idx); cr_w(1, " REGISTERED via Librarian alloc+dual-write (ME0 f64 keystone)\n" as *u8)
40    sys_exit(0)
41    return 0
42}
nx_f64_register.nx source

`nx_f64_register.nx` source
