nx_f64_v8kat_gate.nx source

1// nx_f64_v8kat_gate.nx -- DIFFERENTIAL KAT: replay 4000 V8/hardware-IEEE-754 vectors (knowledge/f64kat.bin, 2// generated on this box by node v22 = real divsd/addsd/mulsd/sqrtsd RNE) through nx_f64_{add,sub,mul,div,sqrt} 3// and demand BIT-EXACT equality (NaN-equivalence for NaN results). Slices: random normals, cancellation, 4// far-exponent alignment, integer ratios (exact/tie), subnormals+overflow, zeros/equal/low-mantissa-ties. 5// This is the EXTERNAL oracle the self-consistent soak gate lacks -- it is what NavierStokes' checksum needs. 6// Record = 7 x i64 LE: a, b, add, sub, mul, div, sqrt(a). Header = count. expect_exit: 0 7// license_tier: ORIGINAL 8import "nx_f64.nx" 9import "nx_f64_div.nx" 10import "nx_f64_sqrt.nx" 11func kw(s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } sys_write(1, s, n); return 0 } 12func kn(v: i64) -> i64 { if v==0 { sys_write(1,"0" as *u8,1); return 0 } var m: i64=v; if m<0 { sys_write(1,"-" as *u8,1); m=0-m } let t: *u8=sys_mmap(24); var k: i64=0; while m>0 { t[k]=(48+(m%10)) as u8; m=m/10; k=k+1 } let o: *u8=sys_mmap(24); var q: i64=k-1; var x: i64=0; while q>=0 { o[x]=t[q]; x=x+1; q=q-1 } sys_write(1,o,x); return 0 } 13// bit-exact match, or both-NaN. 14func kat_ok(got: i64, want: i64) -> i64 { 15 if got == want { return 1 } 16 if nx_f64_is_nan(got) == 1 { if nx_f64_is_nan(want) == 1 { return 1 } } 17 return 0 18} 19func kat_fail(label: *u8, a: i64, b: i64, got: i64, want: i64) -> i64 { 20 kw(" FAIL " as *u8); kw(label) 21 kw(" a=" as *u8); kn(a); kw(" b=" as *u8); kn(b) 22 kw(" got=" as *u8); kn(got); kw(" want=" as *u8); kn(want); kw("\n" as *u8) 23 return 0 24} 25func main(argc: i64, argv: *i64) -> i64 { 26 kw("=== nx_f64_v8kat_gate: nx_f64 ops vs 4000 V8 hardware-IEEE vectors (bit-exact) ===\n" as *u8) 27 let fd: i64 = sys_openat_rd("knowledge/f64kat.bin\x00" as *u8) 28 if fd < 0 { kw("RED: cannot open knowledge/f64kat.bin\n" as *u8); return 1 } 29 let cap: i64 = 1048576 30 let buf: *u8 = sys_mmap(cap) 31 var total: i64 = 0 32 var done: i64 = 0 33 while done == 0 { let n: i64 = sys_read(fd, ((buf as i64) + total) as *u8, cap - total); if n <= 0 { done = 1 } else { total = total + n } } 34 sys_close(fd) 35 let hdr: *i64 = buf as *i64 36 let count: i64 = hdr[0] 37 kw(" vectors: " as *u8); kn(count); kw(" bytes: " as *u8); kn(total); kw("\n" as *u8) 38 if count < 100 { kw("RED: bad header\n" as *u8); return 1 } 39 var fadd: i64 = 0 40 var fsub: i64 = 0 41 var fmul: i64 = 0 42 var fdiv: i64 = 0 43 var fsqrt: i64 = 0 44 var rec: i64 = 0 45 while rec < count { 46 let p: *i64 = ((buf as i64) + 8 + rec * 56) as *i64 47 let a: i64 = p[0] 48 let b: i64 = p[1] 49 let g1: i64 = nx_f64_add(a, b) 50 if kat_ok(g1, p[2]) == 0 { fadd = fadd + 1; if fadd <= 2 { kat_fail("add" as *u8, a, b, g1, p[2]) } } 51 let g2: i64 = nx_f64_sub(a, b) 52 if kat_ok(g2, p[3]) == 0 { fsub = fsub + 1; if fsub <= 2 { kat_fail("sub" as *u8, a, b, g2, p[3]) } } 53 let g3: i64 = nx_f64_mul(a, b) 54 if kat_ok(g3, p[4]) == 0 { fmul = fmul + 1; if fmul <= 2 { kat_fail("mul" as *u8, a, b, g3, p[4]) } } 55 let g4: i64 = nx_f64_div(a, b) 56 if kat_ok(g4, p[5]) == 0 { fdiv = fdiv + 1; if fdiv <= 2 { kat_fail("div" as *u8, a, b, g4, p[5]) } } 57 let g5: i64 = nx_f64_sqrt(a) 58 if kat_ok(g5, p[6]) == 0 { fsqrt = fsqrt + 1; if fsqrt <= 2 { kat_fail("sqrt" as *u8, a, 0, g5, p[6]) } } 59 rec = rec + 1 60 } 61 kw(" mismatches: add=" as *u8); kn(fadd) 62 kw(" sub=" as *u8); kn(fsub) 63 kw(" mul=" as *u8); kn(fmul) 64 kw(" div=" as *u8); kn(fdiv) 65 kw(" sqrt=" as *u8); kn(fsqrt) 66 kw("\n" as *u8) 67 let bad: i64 = fadd + fsub + fmul + fdiv + fsqrt 68 if bad == 0 { kw("=== GREEN: all 5 ops BIT-EXACT with V8 hardware IEEE-754 over 4000 vectors ===\n" as *u8); return 0 } 69 kw("=== RED: " as *u8); kn(bad); kw(" op-results diverge from IEEE (culprit localized above) ===\n" as *u8) 70 return 1 71}