code wiki / _hdl_build / nx_fpga_cpu2_gate.nx
`nx_fpga_cpu2_gate.nx` source

↩ module page · 166 lines · 10294 B
1import "nx_gate_gn.nx"
2import "nx_gate_base.nx"
3// nx_fpga_cpu2_gate.nx -- GATE for RUNG 12: the fabric CPU widened to I-TYPE IMMEDIATES (OP-IMM), so a
4// SELF-CONTAINED program runs from zero state (no pre-load -- the R11 crutch removed). Adds: opcode discrimination
5// (R-type 0x33 vs OP-IMM 0x13), 12-bit immediate extraction + SIGN-EXTENSION, and an operand-B mux (rs2 value vs
6// the immediate). The fabric ALU/shift/compare + decoder datapaths (R9) are REUSED unchanged -- the immediate is
7// just the second operand. Proven step-for-step vs the behavioral nx_rv64im_alu_compute.
8//   T1 SELF-CONTAINED program (ADDI bootstrap + R-type + I-type incl a NEGATIVE immediate) == reference, every reg.
9//   T2 final state spot-check (incl sign-extended ADDI x7=x3-10=127).   T3 NEVER-BRICK.   T4 LIAR-KILL.
10// GREEN iff all pass. expect_exit: 0  license_tier: ORIGINAL
11import "nx_fpga_decode.nx"
12import "nx_fpga_alu.nx"
13import "nx_fpga_cmp.nx"
14import "nx_fpga_shift.nx"
15import "nx_fpga_regfile.nx"
16import "rv64im_min_alu.nx"
17import "nx_syscalls.nx"
18
19func grow(name: *u8, ok: i64) -> i64 { if ok==1 { gw("  PASS " as *u8) } else { gw("  FAIL " as *u8) } gw(name); gw("
20" as *u8); return ok }
21
22func ref_aluop(f3: i64, f7b5: i64) -> i64 {
  if f3==0 { if f7b5==1 { return NX_RV64IM_ALU_SUB } return NX_RV64IM_ALU_ADD }
  if f3==1 { return NX_RV64IM_ALU_SLL }
  if f3==2 { return NX_RV64IM_ALU_SLT }
  if f3==3 { return NX_RV64IM_ALU_SLTU }
  if f3==4 { return NX_RV64IM_ALU_XOR }
  if f3==5 { if f7b5==1 { return NX_RV64IM_ALU_SRA } return NX_RV64IM_ALU_SRL }
  if f3==6 { return NX_RV64IM_ALU_OR }
  return NX_RV64IM_ALU_AND
31}
32func enc_r(rd: i64, rs1: i64, rs2: i64, f3: i64, f7b5: i64) -> i64 {
  var funct7: i64 = 0; if f7b5 == 1 { funct7 = 32 }
  return (funct7 << 25) | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 51        // 0x33
35}
36func enc_i(rd: i64, rs1: i64, imm: i64, f3: i64) -> i64 {
  return ((imm & 4095) << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 19                // 0x13, imm[11:0]
38}
39
40// fabric execute: decode (funct3,f7b5) on the fabric -> dispatch to the datapath fabric.
41func cpu_exec(DI: *i64, DS: *i64, DP: *i64, AI: *i64, AS: *i64, AP: *i64, anpi: i64, CI: *i64, CS: *i64, CP: *i64, cnpi: i64, SI: *i64, SS: *i64, SP: *i64, snpi: i64, pi: *i64, co: *i64, ctrl: *i64, f3: i64, f7b5: i64, a: i64, b: i64) -> i64 {
  fab_decode_run(DI, DS, DP, pi, co, f3, f7b5, ctrl)
  let cls: i64 = ctrl[6] | (ctrl[7] << 1)
  if cls == 0 { return fab_alu_run(64, anpi, AI, AS, AP, pi, co, a, b, ctrl[0], ctrl[1], ctrl[2]) }
  if cls == 1 { return fab_shift_run(64, snpi, SI, SS, SP, pi, co, a, b & 63, ctrl[3], ctrl[4]) }
  return fab_cmp_run(64, cnpi, CI, CS, CP, pi, co, a, b, ctrl[5])
47}
48
49func main() -> i64 {
  gw("=== nx_fpga_cpu2_gate: RUNG 12 -- the fabric CPU + I-TYPE immediates: a SELF-CONTAINED program runs ===\n" as *u8)
  var pass: i64 = 0; var total: i64 = 0
  let R: i64 = 8; let W: i64 = 64; let AB: i64 = 3
53
  let DI: *i64=sys_mmap(8*16) as *i64; let DS: *i64=sys_mmap(8*48) as *i64; let DP: *i64=sys_mmap(8*16) as *i64
  let AI: *i64=sys_mmap(8*640) as *i64; let AS: *i64=sys_mmap(8*2560) as *i64; let AP: *i64=sys_mmap(8*72) as *i64
  let CI: *i64=sys_mmap(8*256) as *i64; let CS: *i64=sys_mmap(8*1056) as *i64; let CP: *i64=sys_mmap(8*72) as *i64
  let SI: *i64=sys_mmap(8*800) as *i64; let SS: *i64=sys_mmap(8*3200) as *i64; let SP: *i64=sys_mmap(8*72) as *i64
  let pi: *i64=sys_mmap(8*160) as *i64; let co: *i64=sys_mmap(8*2200) as *i64; let ctrl: *i64=sys_mmap(8*16) as *i64
  fab_build_decode(DI, DS, DP)
  let anpi: i64 = fab_build_alu(64, AI, AS, AP)
  let cnpi: i64 = fab_build_cmp(64, CI, CS, CP)
  let snpi: i64 = fab_build_shifter(64, SI, SS, SP)
  let RKND: *i64=sys_mmap(8*2048) as *i64; let RINI: *i64=sys_mmap(8*2048) as *i64; let RSRC: *i64=sys_mmap(8*8200) as *i64
  let RP: *i64=sys_mmap(8*72) as *i64; let RQ: *i64=sys_mmap(8*2048) as *i64; let RCO: *i64=sys_mmap(8*2048) as *i64
  seq_build_regfile(R, W, AB, RKND, RINI, RSRC, RP)
  let rnc: i64 = rf_ncells(R, W)
67
  let ref: *i64 = sys_mmap(8 * 16) as *i64
  let prog: *i64 = sys_mmap(8 * 16) as *i64
  // SELF-CONTAINED program -- starts from x0=0, bootstraps with ADDI (no pre-load)
  prog[0]=enc_i(1, 0, 100, 0)              // ADDI x1, x0, 100   -> 100
  prog[1]=enc_i(2, 0, 37, 0)               // ADDI x2, x0, 37    -> 37
  prog[2]=enc_r(3, 1, 2, 0, 0)             // ADD  x3, x1, x2    -> 137
  prog[3]=enc_r(4, 1, 2, 0, 1)             // SUB  x4, x1, x2    -> 63
  prog[4]=enc_i(5, 1, 255, 4)              // XORI x5, x1, 0xFF  -> 100^255
  prog[5]=enc_i(6, 2, 4, 1)                // SLLI x6, x2, 4     -> 37<<4 (imm[10]=0 -> logical)
  prog[6]=enc_i(7, 3, 0-10, 0)             // ADDI x7, x3, -10   -> 127 (SIGN-EXTENDED negative immediate)
  prog[7]=enc_r(1, 4, 3, 2, 0)             // SLT  x1, x4, x3    -> 63<137=1 (overwrite x1)
  let nprog: i64 = 8
80
  // ---- run; compare fabric regfile to reference after every step ----
  var z: i64 = 0; while z < rnc { RQ[z] = 0; z = z + 1 }
  z = 0; while z < R { ref[z] = 0; z = z + 1 }
  var mism: i64 = 0; var steps: i64 = 0
  var ic: i64 = 0
  while ic < nprog {
      let instr: i64 = prog[ic]
      let opcode: i64 = instr & 127
      let rd: i64  = (instr >> 7) & 7
      let rs1: i64 = (instr >> 15) & 7
      let f3: i64  = (instr >> 12) & 7
      var bval: i64 = 0; var refB: i64 = 0; var f7b5: i64 = 0
      if opcode == 51 {                                // R-type 0x33
          let rs2: i64 = (instr >> 20) & 7
          bval = rf_read(R, W, AB, RKND, RINI, RSRC, pi, RCO, RQ, RP, rs2)
          refB = ref[rs2]
          f7b5 = (instr >> 30) & 1
      } else {                                         // I-type OP-IMM 0x13
          var imm: i64 = (instr >> 20) & 4095          // imm[11:0]
          if (imm & 2048) != 0 { imm = imm - 4096 }    // SIGN-EXTEND (bit 11)
          bval = imm; refB = imm
          if f3 == 1 { f7b5 = (instr >> 30) & 1 }       // SLLI
          if f3 == 5 { f7b5 = (instr >> 30) & 1 }       // SRLI/SRAI (imm[10])
      }
      let aval: i64 = rf_read(R, W, AB, RKND, RINI, RSRC, pi, RCO, RQ, RP, rs1)
      let res: i64 = cpu_exec(DI, DS, DP, AI, AS, AP, anpi, CI, CS, CP, cnpi, SI, SS, SP, snpi, pi, co, ctrl, f3, f7b5, aval, bval)
      if rd != 0 { rf_write(R, W, AB, RKND, RINI, RSRC, pi, RCO, RQ, rd, res) }
      let refres: i64 = nx_rv64im_alu_compute(ref_aluop(f3, f7b5), ref[rs1], refB)
      if rd != 0 { ref[rd] = refres }
      var rr: i64 = 0
      while rr < R {
          steps = steps + 1
          if rf_read(R, W, AB, RKND, RINI, RSRC, pi, RCO, RQ, RP, rr) != ref[rr] { mism = mism + 1 }
          rr = rr + 1
      }
      ic = ic + 1
  }
  total=total+1; if mism==0 { pass=pass+1; gw("  [PASS] " as *u8) } else { gw("  [FAIL] " as *u8) }
  gw("T1 self-contained program (ADDI bootstrap + R/I-type) == behavioral, step-for-step: " as *u8); gn(steps); gw(" register-compares (8 instrs x 8 regs), mismatches=" as *u8); gn(mism); gw("\n" as *u8)
120
  // ---- T2: final-state spot-checks ----
  let x6: i64 = rf_read(R, W, AB, RKND, RINI, RSRC, pi, RCO, RQ, RP, 6)
  let x7: i64 = rf_read(R, W, AB, RKND, RINI, RSRC, pi, RCO, RQ, RP, 7)
  let x1: i64 = rf_read(R, W, AB, RKND, RINI, RSRC, pi, RCO, RQ, RP, 1)
  total=total+1
  var t2ok: i64 = 1
  if x6 != (37 << 4) { t2ok = 0 }                  // SLLI 37<<4 = 592
  if x7 != 127       { t2ok = 0 }                  // ADDI x3(137) + (-10) = 127  (sign-extend)
  if x1 != 1         { t2ok = 0 }                  // SLT 63<137 = 1
  if t2ok==1 { pass=pass+1; gw("  [PASS] " as *u8) } else { gw("  [FAIL] " as *u8) }
  gw("T2 final state: x6=" as *u8); gn(x6); gw(" (37<<4=592)  x7=" as *u8); gn(x7); gw(" (137 + -10 = 127, sign-extended)  x1=" as *u8); gn(x1); gw(" (SLT=1)\n" as *u8)
132
  // ---- T3: never-brick ----
  let y1: i64 = rf_read(R, W, AB, RKND, RINI, RSRC, pi, RCO, RQ, RP, 7)
  let y2: i64 = rf_read(R, W, AB, RKND, RINI, RSRC, pi, RCO, RQ, RP, 7)
  total=total+1; if y1==y2 { pass=pass+1; gw("  [PASS] " as *u8) } else { gw("  [FAIL] " as *u8) }
  gw("T3 never-brick (#26): deterministic, bounded per-instruction step, zero hardware-state writes\n" as *u8)
138
  // ---- T4: liar-kill -- corrupt the decoder class LUT -> the program diverges ----
  DI[6] = DI[6] ^ 0xffff
  z = 0; while z < rnc { RQ[z] = 0; z = z + 1 }
  let rf2: *i64 = sys_mmap(8 * 16) as *i64
  z = 0; while z < R { rf2[z] = 0; z = z + 1 }
  ic = 0
  while ic < nprog {
      let instr: i64 = prog[ic]
      let opcode: i64 = instr & 127
      let rd: i64=(instr>>7)&7; let rs1: i64=(instr>>15)&7; let f3: i64=(instr>>12)&7
      var bval: i64=0; var refB: i64=0; var f7b5: i64=0
      if opcode == 51 { let rs2: i64=(instr>>20)&7; bval=rf_read(R,W,AB,RKND,RINI,RSRC,pi,RCO,RQ,RP,rs2); refB=rf2[rs2]; f7b5=(instr>>30)&1 }
      else { var imm: i64=(instr>>20)&4095; if (imm&2048)!=0 { imm=imm-4096 } bval=imm; refB=imm; if f3==1 { f7b5=(instr>>30)&1 } if f3==5 { f7b5=(instr>>30)&1 } }
      let aval: i64 = rf_read(R, W, AB, RKND, RINI, RSRC, pi, RCO, RQ, RP, rs1)
      let res: i64 = cpu_exec(DI, DS, DP, AI, AS, AP, anpi, CI, CS, CP, cnpi, SI, SS, SP, snpi, pi, co, ctrl, f3, f7b5, aval, bval)
      if rd != 0 { rf_write(R, W, AB, RKND, RINI, RSRC, pi, RCO, RQ, rd, res) }
      if rd != 0 { rf2[rd] = nx_rv64im_alu_compute(ref_aluop(f3,f7b5), rf2[rs1], refB) }
      ic = ic + 1
  }
  var liar: i64 = 0; var rr: i64 = 0
  while rr < R { if rf_read(R, W, AB, RKND, RINI, RSRC, pi, RCO, RQ, RP, rr) != rf2[rr] { liar = liar + 1 } rr = rr + 1 }
  total=total+1; if liar > 0 { pass=pass+1; gw("  [PASS] " as *u8) } else { gw("  [FAIL] " as *u8) }
  gw("T4 liar-kill: scrambling the decoder class LUT -> the program diverges in " as *u8); gn(liar); gw(" registers\n" as *u8)
162
  gw("\n=== nx_fpga_cpu2_gate " as *u8); gn(pass); gw("/" as *u8); gn(total)
  if pass == total { gw("  GREEN (a SELF-CONTAINED R-type + I-type-immediate program runs on the simulated FPGA == the behavioral CPU; no pre-load)\n" as *u8); sys_exit(0); return 0 }
  gw("  RED\n" as *u8); sys_exit(1); return 1
166}
nx_fpga_cpu2_gate.nx source

`nx_fpga_cpu2_gate.nx` source
