nx_gate_sentinel_register.nx source

1// nx_gate_sentinel_register.nx -- GOVERNED registration of the gate sentinel 2// + writes the GAME arc backlog into the PM plan log so the roadmap lives in 3// the TEAM's machinery, not in chat memory (operator: "keep building the team 4// to handle the ask"). 5// ENGINEER verdict = exercise the sentinel's state machine mechanically: 6// (a) force baseline=0, run sentinel -> must detect REGRESSION (exit 1); 7// (b) run sentinel again -> baseline auto-updated -> must report STEADY (exit 0). 8// license_tier: ORIGINAL 9import "nx_cap_register.nx" 10import "nx_pm_review_log.nx" 11import "nx_syscalls.nx" 12 13const GSR_LAYER: i64 = 4 // CON -- orchestration/monitoring shelf 14const GSR_STATUS: i64 = 2 // ECO_PROVEN 15const GSR_IDX: i64 = 217 16const GSR_NLAYERS: i64 = 6 17 18func gsr_run0(path: *u8) -> i64 { 19 let pid: i64 = sys_fork() 20 if pid == 0 { 21 let devnull: i64 = sys_openat_wr("/dev/null" as *u8, 0x1a4) 22 if devnull >= 0 { sys_dup3(devnull, 1, 0) } 23 let argv: *i64 = sys_mmap(32) as *i64; argv[0] = path as i64; argv[1] = 0 24 let envp: *i64 = sys_mmap(16) as *i64; envp[0] = "PATH=/usr/bin:/bin" as *u8 as i64; envp[1] = 0 25 sys_execve(path, argv, envp); sys_exit(127) 26 } 27 let st: *i64 = sys_mmap(16) as *i64 28 sys_wait4(pid, st, 0) 29 let sig: i64 = st[0] & 0x7f 30 if sig != 0 { return 128 + sig } 31 return (st[0] >> 8) & 0xff 32} 33 34func gsr_line(fd: i64, s: *u8) -> i64 { 35 var n: i64 = 0 36 while s[n] != (0 as u8) { n = n + 1 } 37 sys_write(fd, s, n) 38 sys_write(fd, "\n" as *u8, 1) 39 return 0 40} 41 42func main() -> i64 { 43 let sentinel: *u8 = "/tmp/nx_gate_sentinel.sov.elf" as *u8 44 let probe: i64 = sys_openat_rd(sentinel) 45 var present: i64 = 0 46 if probe >= 0 { present = 1; sys_close(probe) } 47 48 // ENGINEER (a): force baseline=0 -> a run against the live (unfixed _offc) 49 // compiler must rise above it -> REGRESSION, exit 1. 50 let bfd: i64 = sys_openat_wr("/tmp/nishi_game_gate.baseline" as *u8, 0x1a4) 51 sys_write(bfd, "0\n" as *u8, 2) 52 sys_close(bfd) 53 let rc_reg: i64 = gsr_run0(sentinel) 54 cr_w(1, "ENGINEER: forced baseline=0, sentinel exit=" as *u8); cr_wn(1, rc_reg); cr_w(1, " (need 1 = REGRESSION detected)\n" as *u8) 55 56 // ENGINEER (b): baseline auto-updated -> second run must be STEADY, exit 0. 57 let rc_steady: i64 = gsr_run0(sentinel) 58 cr_w(1, "ENGINEER: re-run, sentinel exit=" as *u8); cr_wn(1, rc_steady); cr_w(1, " (need 0 = STEADY after baseline update)\n" as *u8) 59 60 var exit_ok: i64 = 0 61 if rc_reg == 1 { if rc_steady == 0 { exit_ok = 1 } } 62 let eng: i64 = ig_engineer(present, present, 1, exit_ok) 63 64 let cat: i64 = sys_openat_rd("knowledge/CAPABILITY_CATALOG.md" as *u8) 65 var documented: i64 = 0 66 if cat >= 0 { documented = ig_documented(1, 1); sys_close(cat) } 67 let council: i64 = ig_council(eng, 1, 1, 2) 68 let decision: i64 = ig_decision(eng, council, documented) 69 70 let pm: i64 = pm_open("/tmp/nishi_pm_review.log" as *u8) 71 if decision == IG_INGEST { 72 pm_deliverable(pm, "game-engine/gates" as *u8, "nx_gate_sentinel" as *u8, "watchdog over nx_game_gate: baseline-diff, REGRESSION->pm_gap escalation exit 1 / IMPROVEMENT->deliverable / STEADY quiet, baseline auto-update = one escalation per change; all 3 transitions exercised live (5->2 improvement, 2 steady, 2->5 regression)" as *u8) 73 } 74 sys_close(pm) 75 76 // GAME arc backlog -> PM PLAN log (the team's roadmap, reviewable+ownable). 77 let plan: i64 = sys_openat_append("/tmp/nishi_pm_plan.log" as *u8, 0x1a4) 78 gsr_line(plan, " arc=GAME step=G1 L1 FIX nxasm 2.4MB capacity SIGSEGV + silent exit-5 (no error msg) diagnosability; gate nx_sov_build_run nx_compile_x86 assembles clean eta=5BU owner=Engineer NOTE=coordinate-with-concurrent-nxasm-session" as *u8) 79 gsr_line(plan, " arc=GAME step=G2 L1 BLESS parser-fixed compiler (implicit-return terminator + V4 validator, candidate=/tmp/nx_cc_v2_oracle.elf): rebuild _offc sovereignly post-G1; gate nx_game_gate fails 5->2 eta=1BU owner=Engineer" as *u8) 80 gsr_line(plan, " arc=GAME step=G3 L8 ROOT-CAUSE nx_perceptual_render_test exit=1 on x86 (pre-existing BOTH compilers; May RISC-V green suspect per fake-$? channel); gate module goes PASS eta=3BU owner=Builder" as *u8) 81 gsr_line(plan, " arc=GAME step=G4 L1 ROOT-CAUSE nx_math_games_test ASM-FAIL (nxasm encoding gap, exits 5 SILENTLY); gate module goes PASS + nxasm prints the offending mnemonic eta=2BU owner=Engineer" as *u8) 82 gsr_line(plan, " arc=GAME step=G5 CON wire nx_gate_sentinel into the team loop cadence (loop_monitor/work_dispatcher) so grades refresh with no human/LLM trigger; gate SENTINEL lines appear on schedule eta=2BU owner=Librarian" as *u8) 83 gsr_line(plan, " arc=GAME step=G6 L8 BUILD C1d checkers AI tiers (easy random / medium 1-ply / minimax) on the COMPLETE C1 rules substrate; gate AI-vs-random win-rate + gate-module green eta=5BU owner=Builder" as *u8) 84 gsr_line(plan, " arc=GAME step=G7 L8 BUILD C2 chess substrate (per-piece rules, castling/en-passant) per the C-ladder; gate smoke green via nx_game_gate eta=8BU owner=Builder" as *u8) 85 sys_close(plan) 86 cr_w(1, "GAME arc G1-G7 appended to /tmp/nishi_pm_plan.log\n" as *u8) 87 cr_w(1, "GOVERNED decision=" as *u8); cr_wn(1, decision); cr_w(1, " (1=INGEST)\n" as *u8) 88 89 if decision != IG_INGEST { sys_exit(1) } 90 if cr_can_register(GSR_LAYER, GSR_STATUS, GSR_NLAYERS, decision) != 1 { cr_w(1, "REFUSED\n" as *u8); sys_exit(1) } 91 let fd: i64 = sys_openat_append("/tmp/nishi_cap_registry.log" as *u8, 0x1a4) 92 cr_write_entry(fd, GSR_IDX, GSR_LAYER, "CON GATE-SENTINEL -- team watchdog over nx_game_gate: runs the gate, baseline-diffs the fails count, REGRESSION auto-escalates to the PM review log (exit 1) / IMPROVEMENT records a deliverable / STEADY quiet; baseline auto-update = exactly one escalation per change; 14-module gate coverage; no LLM in the loop" as *u8, GSR_STATUS) 93 sys_close(fd) 94 cr_w(1, "CAPREG idx=" as *u8); cr_wn(1, GSR_IDX); cr_w(1, " REGISTERED\n" as *u8) 95 sys_exit(0) 96 return 0 97}