nx_h264_intra4_gate.nx source
↩ module page · 130 lines · 4888 B
1// nx_h264_intra4_gate.nx -- validate Intra_4x4 (9 modes).
2// Sovereign oracles (no 3rd party):
3// (a) FLAT: all neighbours == C => every mode outputs C everywhere
4// (catches out-of-bounds neighbour reads + tap coefficients that don't sum to 1).
5// (b) mode 0 Vertical: pred[y][x]==top[x] ; mode 1 Horizontal: pred[y][x]==left[y].
6// (c) DDL(3): top ramp top[k]=o+s*k => non-corner pred==o+s*(x+y+1) (linear 3-tap recovery).
7// (d) DDR(4): neighbours from g(x-y)=o+s*(x-y) => pred==o+s*(x-y) for all 16 (proven exact).
8// Modes 5,6,7,8 (VR/HD/VL/HU) get the FLAT check here; their per-value proof is the
9// real-frame reconstruction vs ffmpeg (capstone oracle). HONEST: stated, not hidden.
10// Exit 0/1. license_tier: ORIGINAL
11import "nx_syscalls.nx"
12import "nx_h264_intra.nx"
13
14func gp(fd: i64, s: *u8) -> i64 {
15 var n: i64 = 0
16 while s[n] != (0 as u8) { n = n + 1 }
17 sys_write(1, s, n); if fd > 0 { sys_write(fd, s, n) }
18 return 0
19}
20func gnum(fd: i64, v: i64) -> i64 {
21 let bb: *u8 = sys_mmap(28)
22 var m: i64 = v
23 if m < 0 { sys_write(1, "-\x00" as *u8, 1); if fd > 0 { sys_write(fd, "-\x00" as *u8, 1) } m = 0 - m }
24 let t: *u8 = sys_mmap(28); var k: i64 = 0
25 if m == 0 { t[0] = 48 as u8; k = 1 }
26 while m > 0 { t[k] = (48 + (m % 10)) as u8; m = m / 10; k = k + 1 }
27 var i: i64 = 0
28 while i < k { bb[i] = t[k - 1 - i]; i = i + 1 }
29 sys_write(1, bb, k); if fd > 0 { sys_write(fd, bb, k) }
30 return 0
31}
32
33func main() -> i64 {
34 let fd: i64 = sys_openat_append("knowledge/status/h264_intra4_gate.log\x00" as *u8, 0x1a4)
35 gp(fd, "H264-INTRA4-GATE (9 modes)\n\x00" as *u8)
36 var ok: i64 = 1
37
38 // (a) FLAT for all 9 modes
39 let t: *i64 = sys_mmap(8*8) as *i64
40 let l: *i64 = sys_mmap(4*8) as *i64
41 let pred: *i64 = sys_mmap(16*8) as *i64
42 var flatpass: i64 = 0
43 var mode: i64 = 0
44 while mode < 9 {
45 var i: i64 = 0
46 while i < 8 { t[i] = 137; i = i + 1 }
47 i = 0
48 while i < 4 { l[i] = 137; i = i + 1 }
49 nx_intra4x4_pred_full(mode, t, l, 137, 1, 1, pred)
50 var allc: i64 = 1
51 i = 0
52 while i < 16 { if pred[i] != 137 { allc = 0 } i = i + 1 }
53 if allc == 1 { flatpass = flatpass + 1 }
54 mode = mode + 1
55 }
56 gp(fd, " flat->flat modes passing=\x00" as *u8); gnum(fd, flatpass); gp(fd, "/9\n\x00" as *u8)
57 if flatpass != 9 { ok = 0 }
58
59 // (b) mode 0 Vertical + mode 1 Horizontal exact
60 var i: i64 = 0
61 while i < 8 { t[i] = 10 + i*7; i = i + 1 }
62 i = 0
63 while i < 4 { l[i] = 200 - i*9; i = i + 1 }
64 nx_intra4x4_pred_full(0, t, l, 50, 1, 1, pred)
65 var vok: i64 = 1
66 var y: i64 = 0
67 while y < 4 { var x: i64 = 0; while x < 4 { if pred[y*4+x] != t[x] { vok = 0 } x = x + 1 } y = y + 1 }
68 nx_intra4x4_pred_full(1, t, l, 50, 1, 1, pred)
69 var hok: i64 = 1
70 y = 0
71 while y < 4 { var x: i64 = 0; while x < 4 { if pred[y*4+x] != l[y] { hok = 0 } x = x + 1 } y = y + 1 }
72 gp(fd, " mode0 V exact=\x00" as *u8); gnum(fd, vok); gp(fd, " mode1 H exact=\x00" as *u8); gnum(fd, hok); gp(fd, "\n\x00" as *u8)
73 if vok != 1 { ok = 0 }
74 if hok != 1 { ok = 0 }
75
76 // (c) DDL(3) top-ramp reproduction
77 let o3: i64 = 20
78 let s3: i64 = 8
79 i = 0
80 while i < 8 { t[i] = o3 + s3*i; i = i + 1 }
81 nx_intra4x4_pred_full(3, t, l, 50, 1, 1, pred)
82 var ddl: i64 = 1
83 y = 0
84 while y < 4 {
85 var x: i64 = 0
86 while x < 4 {
87 var want: i64 = o3 + s3*(x+y+1)
88 if x == 3 { if y == 3 { want = (t[6] + 3*t[7] + 2) >> 2 } }
89 if pred[y*4+x] != want { ddl = 0 }
90 x = x + 1
91 }
92 y = y + 1
93 }
94 gp(fd, " DDL(3) ramp-reproduction exact=\x00" as *u8); gnum(fd, ddl); gp(fd, "\n\x00" as *u8)
95 if ddl != 1 { ok = 0 }
96
97 // (d) DDR(4): neighbours on plane g(x-y)=o+s*(x-y)
98 let o4: i64 = 128
99 let s4: i64 = 10
100 i = 0
101 while i < 8 { t[i] = o4 + s4*(i+1); i = i + 1 } // p[i,-1] = g(i+1)
102 i = 0
103 while i < 4 { l[i] = o4 + s4*(0-1-i); i = i + 1 } // p[-1,i] = g(-1-i)
104 nx_intra4x4_pred_full(4, t, l, o4, 1, 1, pred) // tl = g(0)=o4
105 var ddr: i64 = 0
106 y = 0
107 while y < 4 {
108 var x: i64 = 0
109 while x < 4 {
110 if pred[y*4+x] == o4 + s4*(x-y) { ddr = ddr + 1 }
111 x = x + 1
112 }
113 y = y + 1
114 }
115 gp(fd, " DDR(4) plane-reproduction exact=\x00" as *u8); gnum(fd, ddr); gp(fd, "/16\n\x00" as *u8)
116 if ddr != 16 { ok = 0 }
117
118 gp(fd, " NOTE modes 5,6,7,8 (VR/HD/VL/HU): flat-gated here; per-value proof = real-frame vs ffmpeg\n\x00" as *u8)
119
120 if ok == 1 {
121 gp(fd, "H264-INTRA4-GATE result=ALL-PASS verdict=GREEN\n\x00" as *u8)
122 if fd > 0 { sys_close(fd) }
123 sys_exit(0)
124 return 0
125 }
126 gp(fd, "H264-INTRA4-GATE result=FAIL verdict=RED\n\x00" as *u8)
127 if fd > 0 { sys_close(fd) }
128 sys_exit(1)
129 return 1
130}