code wiki / _hdl_build / nx_hw_envelope.nx
nx_hw_envelope.nx source
↩ module page · 371 lines · 15728 B
1// nx_hw_envelope.nx -- HARDWARE-AWARE MODEL ROUTER (2026-07-23; operator: "hardware aware component
2// if we shift to larger or smaller systems so future nishi os can run on anything from a phone to a
3// supercomputer"). Measures the HOST envelope (RAM via /proc/meminfo, logical cores via /proc/cpuinfo,
4// both STREAM-read because /proc stat sizes lie) and picks the maker/bench model roster for this
5// hardware TIER from the sovereign plane knowledge/store/hwtier- (rule 11: thresholds AND rosters are
6// DATA -- rows `tier|min_gb|maker|bench|note`, pipe-packed payload = the declared-canonical store row
7// format). External models appear ONLY in the bench column and are marked BENCH-ONLY (the
8// external-reimpls-bench-only law); the sovereign maker column is always the primary. Fail-closed:
9// absent/empty plane = RED exit 1; no tier fits the measured RAM = RED exit 3; VRAM reports
10// UNMEASURED in v1 (no honest sovereign probe yet), never guessed.
11// nx_hw_envelope probe -- measure host -> JSON
12// nx_hw_envelope route [planeprefix] -- probe + tier-match -> routing JSON (+ hw_envelope.out)
13// nx_hw_envelope selftest -- hermetic teeth (gv lib)
14// license_tier: ORIGINAL expect_exit: 0 No hw writes (Rule 26).
15import "nx_syscalls.nx"
16import "nx_gate_verdict.nx"
17import "nx_sovjson_lib.nx"
18import "nx_store_seed_lib.nx"
19import "nx_seg_store.nx"
20
21const HW_CAP: i64 = 262144
22const HW_PLANE: i64 = 1048576
23const HW_KB_PER_GB: i64 = 1048576
24const HW_SLOT: i64 = 16
25const HW_MAXROWS: i64 = 32
26const HW_ROWI: i64 = 9
27const HW_ROWBYTES: i64 = 2304
28const HW_RES: i64 = 80
29const HW_USAGE: i64 = 2
30const HW_NOFIT: i64 = 3
31
32func hw_read_stream(path: *u8, buf: *u8, cap: i64) -> i64 {
33 let fd: i64 = sys_openat_rd(path)
34 if fd < 0 { return 0 - 1 }
35 var t: i64 = 0
36 var go: i64 = 1
37 while go == 1 {
38 if t >= cap { go = 0 } else {
39 let r: i64 = sys_read(fd, ((buf as i64) + t) as *u8, cap - t)
40 if r <= 0 { go = 0 } else { t = t + r }
41 }
42 }
43 sys_close(fd)
44 return t
45}
46
47// value of the digit-run following the first occurrence of `key`; -1 if key/digits absent
48func hw_num_after(q: *u8, n: i64, key: *u8) -> i64 {
49 let kl: i64 = sj_vlen(key)
50 var at: i64 = 0 - 1
51 var i: i64 = 0
52 while i + kl <= n {
53 if at < 0 {
54 var m: i64 = 1
55 var k: i64 = 0
56 while k < kl { if q[i+k] != key[k] { m = 0; k = kl } else { k = k + 1 } }
57 if m == 1 { at = i + kl }
58 }
59 i = i + 1
60 }
61 if at < 0 { return 0 - 1 }
62 var j: i64 = at
63 var s: i64 = 1
64 while s == 1 {
65 if j >= n { return 0 - 1 }
66 var c: i64 = q[j] as i64
67 if c >= 48 { if c <= 57 { s = 0 } else { j = j + 1 } } else { j = j + 1 }
68 }
69 var v: i64 = 0
70 var go: i64 = 1
71 while go == 1 {
72 if j >= n { go = 0 } else {
73 var d: i64 = q[j] as i64
74 if d >= 48 { if d <= 57 { v = v * 10 + (d - 48); j = j + 1 } else { go = 0 } } else { go = 0 }
75 }
76 }
77 return v
78}
79
80func hw_count_linestart(q: *u8, n: i64, lit: *u8) -> i64 {
81 let ll: i64 = sj_vlen(lit)
82 var c: i64 = 0
83 var i: i64 = 0
84 while i + ll <= n {
85 var at_ls: i64 = 0
86 if i == 0 { at_ls = 1 } else { if q[i-1] == (10 as u8) { at_ls = 1 } }
87 if at_ls == 1 {
88 var m: i64 = 1
89 var k: i64 = 0
90 while k < ll { if q[i+k] != lit[k] { m = 0; k = ll } else { k = k + 1 } }
91 if m == 1 { c = c + 1 }
92 }
93 i = i + 1
94 }
95 return c
96}
97
98// ---------- pure tier picker (hermetically gateable): best fit = LARGEST min_gb <= ram_gb ----------
99func hw_pick(mins: *i64, n: i64, ram_gb: i64) -> i64 {
100 var best: i64 = 0 - 1
101 var bestmin: i64 = 0 - 1
102 var i: i64 = 0
103 while i < n {
104 if mins[i] <= ram_gb { if mins[i] > bestmin { bestmin = mins[i]; best = i } }
105 i = i + 1
106 }
107 return best
108}
109
110// parse one plane line: payload = last tab field, pipes tier|min_gb|maker|bench|note.
111// res = [tier_s,tier_e, maker_s,maker_e, bench_s,bench_e, note_s,note_e, min_gb]; 1 ok
112func hw_row(q: *u8, ls: i64, le: i64, res: *i64) -> i64 {
113 var lt: i64 = 0 - 1
114 var i: i64 = ls
115 while i < le { if q[i] == (9 as u8) { lt = i } i = i + 1 }
116 if lt < 0 { return 0 }
117 let ps: i64 = lt + 1
118 let pp: *i64 = sys_mmap(64) as *i64
119 var np: i64 = 0
120 i = ps
121 while i < le { if q[i] == (124 as u8) { if np < 6 { pp[np] = i; np = np + 1 } } i = i + 1 }
122 if np < 4 { return 0 }
123 res[0] = ps
124 res[1] = pp[0]
125 res[8] = sj_atoi_span(q, pp[0] + 1, pp[1])
126 res[2] = pp[1] + 1
127 res[3] = pp[2]
128 res[4] = pp[2] + 1
129 res[5] = pp[3]
130 res[6] = pp[3] + 1
131 res[7] = le
132 return 1
133}
134
135// TS09/F960: emit the tier's MAKER SET as a launcher-consumable list. The plane's maker column may carry
136// an optional label prefix and '+'-joined members (e.g. `ensemble3:a.gguf+b.gguf+c.gguf`); this yields
137// `a.gguf b.gguf c.gguf` so a caller does `nx_autofix_ensemble <manifest> $(nx_hw_envelope makers)` and the
138// SAME loop runs phone->supercomputer with only a hwtier- row changing. Paths are emitted VERBATIM from the
139// plane (rule 11: the data is the authority -- put absolute paths in the row if the caller needs them).
140func hw_makers(d: *u8, o: i64, q: *u8, s: i64, e: i64) -> i64 {
141 var st: i64 = s
142 var seen: i64 = 0
143 var i: i64 = s
144 while i < e { if seen == 0 { if q[i] == (58 as u8) { st = i + 1; seen = 1 } } i = i + 1 }
145 var oo: i64 = o
146 var m: i64 = st
147 var first: i64 = 1
148 while m < e {
149 var me: i64 = m
150 var scan: i64 = 1
151 while scan == 1 { if me >= e { scan = 0 } else { if q[me] == (43 as u8) { scan = 0 } else { me = me + 1 } } }
152 if me > m {
153 if first == 0 { d[oo] = 32 as u8; oo = oo + 1 }
154 first = 0
155 var k: i64 = m
156 while k < me { d[oo] = q[k]; oo = oo + 1; k = k + 1 }
157 }
158 m = me + 1
159 }
160 return oo
161}
162
163func hw_span(d: *u8, o: i64, q: *u8, s: i64, e: i64) -> i64 {
164 var i: i64 = s
165 var oo: i64 = o
166 while i < e { d[oo] = q[i]; oo = oo + 1; i = i + 1 }
167 return oo
168}
169
170// out[0]=ram_gb out[1]=ram_kb out[2]=cores(-1 unmeasured); 0 ok
171func hw_probe(out: *i64) -> i64 {
172 let mi: *u8 = sys_mmap(HW_CAP)
173 let mn: i64 = hw_read_stream("/proc/meminfo\x00" as *u8, mi, HW_CAP)
174 if mn <= 0 { return 0 - 1 }
175 let kb: i64 = hw_num_after(mi, mn, "MemTotal:" as *u8)
176 if kb <= 0 { return 0 - 1 }
177 let ci: *u8 = sys_mmap(HW_CAP)
178 let cn: i64 = hw_read_stream("/proc/cpuinfo\x00" as *u8, ci, HW_CAP)
179 var cores: i64 = 0 - 1
180 if cn > 0 { cores = hw_count_linestart(ci, cn, "processor" as *u8) }
181 out[0] = kb / HW_KB_PER_GB
182 out[1] = kb
183 out[2] = cores
184 return 0
185}
186
187func main(argc: i64, argv: *i64) -> i64 {
188 if argc < 2 {
189 sj_werr("usage: nx_hw_envelope probe | route [planeprefix] | selftest\n" as *u8)
190 sys_exit(HW_USAGE)
191 return HW_USAGE
192 }
193 let verb: *u8 = argv[1] as *u8
194 let vl: i64 = sj_vlen(verb)
195
196 if sj_lit_eq(verb, 0, vl, "selftest" as *u8) == 1 {
197 let ctr: *i64 = gv_ctr()
198 gv_head("nx_hw_envelope selftest -- pure tier picker + row/proc parsers (hermetic)" as *u8)
199 let mins: *i64 = sys_mmap(64) as *i64
200 mins[0] = 0
201 mins[1] = 4
202 mins[2] = 16
203 mins[3] = 48
204 mins[4] = 512
205 var ok1: i64 = 0
206 if hw_pick(mins, 5, 16) == 2 { ok1 = 1 }
207 gv_check("T1 exact boundary ram==min picks that tier" as *u8, ok1, ctr)
208 var ok2: i64 = 0
209 if hw_pick(mins, 5, 32) == 2 { ok2 = 1 }
210 gv_check("T2 between tiers picks the lower tier" as *u8, ok2, ctr)
211 var ok3: i64 = 0
212 if hw_pick(mins, 5, 999) == 4 { ok3 = 1 }
213 gv_check("T3 above all mins picks the largest tier" as *u8, ok3, ctr)
214 let mins2: *i64 = sys_mmap(32) as *i64
215 mins2[0] = 4
216 mins2[1] = 16
217 var ok4: i64 = 0
218 if hw_pick(mins2, 2, 2) == (0 - 1) { ok4 = 1 }
219 gv_check("T4 below-all fail-closed returns no-fit" as *u8, ok4, ctr)
220 let l5: *u8 = "9\x09a\x09put\x09laptop\x09-\x09laptop|16|makerA|benchB|noteC" as *u8
221 let r5: *i64 = sys_mmap(HW_RES) as *i64
222 var ok5: i64 = 0
223 if hw_row(l5, 0, sj_vlen(l5), r5) == 1 { if r5[8] == 16 { if sj_lit_eq(l5, r5[4], r5[5], "benchB" as *u8) == 1 { ok5 = 1 } } }
224 gv_check("T5 plane row parse: tier/min_gb/bench extracted" as *u8, ok5, ctr)
225 let l6: *u8 = "9\x09a\x09put\x09x\x09-\x09no-pipes-here" as *u8
226 var ok6: i64 = 0
227 if hw_row(l6, 0, sj_vlen(l6), r5) == 0 { ok6 = 1 }
228 gv_check("T6 malformed row rejected" as *u8, ok6, ctr)
229 let l7: *u8 = "MemFree: 9 kB\nMemTotal: 512 kB\n" as *u8
230 var ok7: i64 = 0
231 if hw_num_after(l7, sj_vlen(l7), "MemTotal:" as *u8) == 512 { ok7 = 1 }
232 gv_check("T7 meminfo digit-run parse" as *u8, ok7, ctr)
233 let l8: *u8 = "processor : 0\nfoo processor\nprocessor : 1\n" as *u8
234 var ok8: i64 = 0
235 if hw_count_linestart(l8, sj_vlen(l8), "processor" as *u8) == 2 { ok8 = 1 }
236 gv_check("T8 core count = line-start processor entries only" as *u8, ok8, ctr)
237 let mb: *u8 = sys_mmap(HW_CAP)
238 let e9: *u8 = "ensemble3:a.gguf+b.gguf+c.gguf" as *u8
239 var n9: i64 = hw_makers(mb, 0, e9, 0, sj_vlen(e9))
240 mb[n9] = 0 as u8
241 gv_check("T9 makers: labelled '+'-joined set -> space-separated list" as *u8, sj_lit_eq(mb, 0, n9, "a.gguf b.gguf c.gguf" as *u8), ctr)
242 let e10: *u8 = "solo.gguf" as *u8
243 var n10: i64 = hw_makers(mb, 0, e10, 0, sj_vlen(e10))
244 mb[n10] = 0 as u8
245 gv_check("T10 makers: bare single model passes through unchanged" as *u8, sj_lit_eq(mb, 0, n10, "solo.gguf" as *u8), ctr)
246 let e11: *u8 = "pair:/abs/x.gguf+/abs/y.gguf" as *u8
247 var n11: i64 = hw_makers(mb, 0, e11, 0, sj_vlen(e11))
248 mb[n11] = 0 as u8
249 gv_check("T11 makers: absolute paths emitted verbatim (plane is the authority)" as *u8, sj_lit_eq(mb, 0, n11, "/abs/x.gguf /abs/y.gguf" as *u8), ctr)
250 let rc: i64 = gv_verdict("HW-ENVELOPE-SELFTEST" as *u8, ctr, "tier pick + parsers sound, fail-closed no-fit" as *u8)
251 sys_exit(rc)
252 return rc
253 }
254
255 if sj_lit_eq(verb, 0, vl, "probe" as *u8) == 1 {
256 let pv: *i64 = sys_mmap(32) as *i64
257 if hw_probe(pv) != 0 { sj_werr("HW-ENVELOPE RED: /proc probe failed\n" as *u8); sys_exit(1); return 1 }
258 let jb: *u8 = sys_mmap(HW_CAP)
259 var j: i64 = 0
260 j = sj_cat(jb, j, "{\x22organ\x22:\x22nx_hw_envelope\x22,\x22ram_gb\x22:" as *u8)
261 j = sj_catn(jb, j, pv[0])
262 j = sj_cat(jb, j, ",\x22ram_kb\x22:" as *u8)
263 j = sj_catn(jb, j, pv[1])
264 j = sj_cat(jb, j, ",\x22cores\x22:" as *u8)
265 j = sj_catn(jb, j, pv[2])
266 j = sj_cat(jb, j, ",\x22vram\x22:\x22UNMEASURED-v1\x22}" as *u8)
267 jb[j] = 10 as u8
268 sys_write(1, jb, j + 1)
269 sys_exit(0)
270 return 0
271 }
272
273 if sj_lit_eq(verb, 0, vl, "makers" as *u8) == 1 {
274 var pfx2: *u8 = "knowledge/store/hwtier-\x00" as *u8
275 if argc >= 3 { pfx2 = argv[2] as *u8 }
276 let pv2: *i64 = sys_mmap(32) as *i64
277 if hw_probe(pv2) != 0 { sj_werr("HW-ENVELOPE RED: /proc probe failed\n" as *u8); sys_exit(1); return 1 }
278 let pb2: *u8 = sys_mmap(HW_PLANE)
279 let pn2: i64 = sts_load(pfx2, pb2, HW_PLANE - HW_CAP)
280 if pn2 <= 0 { sj_werr("HW-ENVELOPE RED: hwtier plane absent or empty\n" as *u8); sys_exit(1); return 1 }
281 let rows2: *i64 = sys_mmap(HW_ROWBYTES) as *i64
282 let mins2: *i64 = sys_mmap(HW_MAXROWS * 8) as *i64
283 var nr2: i64 = 0
284 var i2: i64 = 0
285 while i2 < pn2 {
286 let ls2: i64 = i2
287 let le2: i64 = sj_le(pb2, ls2, pn2)
288 i2 = le2 + 1
289 let rr2: *i64 = sys_mmap(HW_RES) as *i64
290 if hw_row(pb2, ls2, le2, rr2) == 1 { if nr2 < HW_MAXROWS {
291 var k2: i64 = 0
292 while k2 < HW_ROWI { rows2[nr2 * HW_ROWI + k2] = rr2[k2]; k2 = k2 + 1 }
293 mins2[nr2] = rr2[8]
294 nr2 = nr2 + 1
295 } }
296 }
297 if nr2 == 0 { sj_werr("HW-ENVELOPE RED: plane held no parseable tier rows\n" as *u8); sys_exit(1); return 1 }
298 let pk2: i64 = hw_pick(mins2, nr2, pv2[0])
299 if pk2 < 0 { sj_werr("HW-ENVELOPE RED: no tier fits measured ram (fail-closed)\n" as *u8); sys_exit(HW_NOFIT); return HW_NOFIT }
300 let b2: i64 = pk2 * HW_ROWI
301 let ob2: *u8 = sys_mmap(HW_CAP)
302 var oo2: i64 = hw_makers(ob2, 0, pb2, rows2[b2+2], rows2[b2+3])
303 ob2[oo2] = 10 as u8
304 sys_write(1, ob2, oo2 + 1)
305 sys_exit(0)
306 return 0
307 }
308
309 if sj_lit_eq(verb, 0, vl, "route" as *u8) == 1 {
310 var pfx: *u8 = "knowledge/store/hwtier-\x00" as *u8
311 if argc >= 3 { pfx = argv[2] as *u8 }
312 let pv: *i64 = sys_mmap(32) as *i64
313 if hw_probe(pv) != 0 { sj_werr("HW-ENVELOPE RED: /proc probe failed\n" as *u8); sys_exit(1); return 1 }
314 let pb: *u8 = sys_mmap(HW_PLANE)
315 let pn: i64 = sts_load(pfx, pb, HW_PLANE - HW_CAP)
316 if pn <= 0 { sj_werr("HW-ENVELOPE RED: hwtier plane absent or empty (fail-closed, no roster without data)\n" as *u8); sys_exit(1); return 1 }
317 let rows: *i64 = sys_mmap(HW_ROWBYTES) as *i64
318 let mins: *i64 = sys_mmap(HW_MAXROWS * 8) as *i64
319 var nrows: i64 = 0
320 var i: i64 = 0
321 while i < pn {
322 let ls: i64 = i
323 let le: i64 = sj_le(pb, ls, pn)
324 i = le + 1
325 let rr: *i64 = sys_mmap(HW_RES) as *i64
326 if hw_row(pb, ls, le, rr) == 1 { if nrows < HW_MAXROWS {
327 var k: i64 = 0
328 while k < HW_ROWI { rows[nrows * HW_ROWI + k] = rr[k]; k = k + 1 }
329 mins[nrows] = rr[8]
330 nrows = nrows + 1
331 } }
332 }
333 if nrows == 0 { sj_werr("HW-ENVELOPE RED: plane held no parseable tier rows\n" as *u8); sys_exit(1); return 1 }
334 let pick: i64 = hw_pick(mins, nrows, pv[0])
335 if pick < 0 {
336 sj_werr("HW-ENVELOPE RED: no tier fits measured ram (fail-closed)\n" as *u8)
337 sys_exit(HW_NOFIT)
338 return HW_NOFIT
339 }
340 let b: i64 = pick * HW_ROWI
341 let jb: *u8 = sys_mmap(HW_CAP)
342 var j: i64 = 0
343 j = sj_cat(jb, j, "{\x22organ\x22:\x22nx_hw_envelope\x22,\x22ram_gb\x22:" as *u8)
344 j = sj_catn(jb, j, pv[0])
345 j = sj_cat(jb, j, ",\x22cores\x22:" as *u8)
346 j = sj_catn(jb, j, pv[2])
347 j = sj_cat(jb, j, ",\x22vram\x22:\x22UNMEASURED-v1\x22,\x22tier\x22:\x22" as *u8)
348 j = hw_span(jb, j, pb, rows[b], rows[b+1])
349 j = sj_cat(jb, j, "\x22,\x22min_gb\x22:" as *u8)
350 j = sj_catn(jb, j, rows[b+8])
351 j = sj_cat(jb, j, ",\x22maker\x22:\x22" as *u8)
352 j = hw_span(jb, j, pb, rows[b+2], rows[b+3])
353 j = sj_cat(jb, j, "\x22,\x22bench\x22:\x22" as *u8)
354 j = hw_span(jb, j, pb, rows[b+4], rows[b+5])
355 j = sj_cat(jb, j, "\x22,\x22bench_role\x22:\x22BENCH-ONLY-external\x22,\x22note\x22:\x22" as *u8)
356 j = hw_span(jb, j, pb, rows[b+6], rows[b+7])
357 j = sj_cat(jb, j, "\x22,\x22rows\x22:" as *u8)
358 j = sj_catn(jb, j, nrows)
359 j = sj_cat(jb, j, "}" as *u8)
360 jb[j] = 10 as u8
361 sys_write(1, jb, j + 1)
362 let fd: i64 = sys_openat_wr("knowledge/status/hw_envelope.out\x00" as *u8, 420)
363 if fd >= 0 { sys_write(fd, jb, j + 1); sys_close(fd) }
364 sys_exit(0)
365 return 0
366 }
367
368 sj_werr("usage: nx_hw_envelope probe | route [planeprefix] | selftest\n" as *u8)
369 sys_exit(HW_USAGE)
370 return HW_USAGE
371}