nx_linkqual_cycles.nx source
↩ module page · 130 lines · 5144 B
1// nx_linkqual_cycles.nx -- CYCLE-ACCURATE hot-path measurement of the
2// link-quality substrate using the sovereign __rdtsc() intrinsic. This is
3// the hardware-limit metric: reference-cycles per op straight off the CPU's
4// timestamp counter, with NO per-op syscall in the loop (two reads bracket
5// N calls, amortized).
6//
7// HONEST METHOD:
8// - a warmup pass is discarded (caches/branch-predictors warm).
9// - inputs vary per-iteration so the work can't be constant-folded.
10// - rdtsc measures INVARIANT-TSC reference cycles (the constant base-rate
11// counter), NOT turbo-scaled retired core cycles -- so we ALSO bracket
12// the identical loop with the microsecond clock and derive the effective
13// TSC GHz (cycles/ns). If that GHz matches the CPU's base clock, the two
14// independent clocks agree and the numbers are trustworthy (1:1 cross-
15// validation, [[feedback-1to1-proof-no-proxy-2026-05-28]]).
16//
17// license_tier: ORIGINAL
18
19import "nx_linkqual.nx"
20const K_MAGIC_2000000: i64 = 2000000
21const K_MAGIC_1000000000: i64 = 1000000000
22const K_MAGIC_200000: i64 = 200000
23const K_MAGIC_2654435761: i64 = 2654435761
24
25func bdec(n: i64) -> i64 {
26 if n == 0 { sys_write(1, "0" as *u8, 1); return 0 }
27 var m: i64 = n
28 if m < 0 { sys_write(1, "-" as *u8, 1); m = 0 - m }
29 let d: *u8 = sys_mmap(24)
30 var k: i64 = 0
31 while m > 0 { d[k] = (0x30 + (m % 10)) as u8; m = m / 10; k = k + 1 }
32 var i: i64 = k - 1
33 while i >= 0 { let one: *u8 = sys_mmap(1); one[0] = d[i]; sys_write(1, one, 1); i = i - 1 }
34 return 0
35}
36// fixed-point: print n/100 as D.DD
37func bcenti(n: i64) -> i64 {
38 bdec(n / 100); sys_write(1, ".", 1)
39 let f: i64 = n % 100
40 if f < 10 { sys_write(1, "0", 1) }
41 bdec(f); return 0
42}
43// label: cycles total + us total over N iters -> cyc/op, ns/op, GHz.
44func report(label: *u8, llen: i64, n: i64, cyc: i64, us: i64) -> i64 {
45 sys_write(1, label, llen)
46 let cyc_op: i64 = cyc / n
47 sys_write(1, " ", 2); bdec(cyc_op); sys_write(1, " cyc/op, ", 10)
48 let ns_op: i64 = (us * 1000) / n
49 bdec(ns_op); sys_write(1, " ns/op, ", 9)
50 // effective TSC GHz = cycles / ns ; print as centi-GHz (x.xx)
51 var cghz: i64 = 0
52 if us > 0 { cghz = (cyc * 100) / (us * 1000) }
53 sys_write(1, "TSC=", 4); bcenti(cghz); sys_write(1, " GHz\n", 5)
54 return 0
55}
56
57func main() -> i64 {
58 let N: i64 = K_MAGIC_2000000
59
60 // ---- rdtsc read-pair overhead (median-ish: min of a few) ----
61 var ov: i64 = K_MAGIC_1000000000
62 var t: i64 = 0
63 while t < 1000 {
64 let a: i64 = __rdtsc()
65 let b: i64 = __rdtsc()
66 let d: i64 = b - a
67 if d < ov { ov = d }
68 t = t + 1
69 }
70 sys_write(1, "NX-LINKQUAL CYCLE BENCH (sovereign __rdtsc, 1:1 on this hardware)\n", 66)
71 sys_write(1, "-----------------------------------------------------------------\n", 66)
72 sys_write(1, " rdtsc read-pair overhead (min of 1000): ", 42); bdec(ov); sys_write(1, " cyc\n\n", 6)
73
74 // ---- warmup (discarded) ----
75 let wf: *LinkFlow = lq_flow_new()
76 var w: i64 = 0
77 while w < K_MAGIC_200000 { lq_on_arrival(wf, w, w + 10 + (w & 7)); lq_record_latency(wf, (w & 1023) + 1); w = w + 1 }
78
79 // ---- 1: lq_on_arrival (RFC3550 jitter) ----
80 let g: *LinkFlow = lq_flow_new()
81 let c0: i64 = __rdtsc()
82 let u0: i64 = sys_now_us()
83 var i: i64 = 0
84 // realistic jitter: unpredictable-sign transit deltas (bit-mixed), so the
85 // abs() branch mispredicts ~50% like real network jitter -- not a synthetic
86 // monotone input the predictor would ace.
87 while i < N { let off: i64 = ((i * K_MAGIC_2654435761) >> 13) & 63; lq_on_arrival(g, i, i + 10 + off); i = i + 1 }
88 let u1: i64 = sys_now_us()
89 let c1: i64 = __rdtsc()
90 report("jitter (lq_on_arrival): ", 27, N, c1 - c0, u1 - u0)
91
92 // ---- 2: lq_record_latency (HDR quantile bucket) ----
93 let h: *LinkFlow = lq_flow_new()
94 let c2: i64 = __rdtsc()
95 let u2: i64 = sys_now_us()
96 i = 0
97 while i < N { lq_record_latency(h, (i & 1023) + 1); i = i + 1 }
98 let u3: i64 = sys_now_us()
99 let c3: i64 = __rdtsc()
100 report("latency (lq_record_latency):", 29, N, c3 - c2, u3 - u2)
101
102 // ---- 3: lq_on_rtt (RFC6298 smoothing) ----
103 let r: *LinkFlow = lq_flow_new()
104 let c4: i64 = __rdtsc()
105 let u4: i64 = sys_now_us()
106 i = 0
107 while i < N { lq_on_rtt(r, 20 + (i & 63)); i = i + 1 }
108 let u5: i64 = sys_now_us()
109 let c5: i64 = __rdtsc()
110 report("rtt (lq_on_rtt): ", 27, N, c5 - c4, u5 - u4)
111
112 // ---- 4: full per-packet (seq + arrival + record) ----
113 let p: *LinkFlow = lq_flow_new()
114 let c6: i64 = __rdtsc()
115 let u6: i64 = sys_now_us()
116 i = 0
117 while i < N {
118 let off: i64 = ((i * K_MAGIC_2654435761) >> 13) & 63
119 lq_on_seq(p, i)
120 lq_on_arrival(p, i, i + 10 + off)
121 lq_record_latency(p, (i & 1023) + 1)
122 i = i + 1
123 }
124 let u7: i64 = sys_now_us()
125 let c7: i64 = __rdtsc()
126 report("per-pkt (seq+arr+rec): ", 27, N, c7 - c6, u7 - u6)
127
128 sys_write(1, "\n (cyc/op = reference TSC cycles; if TSC GHz ~= CPU base clock, both clocks agree)\n", 84)
129 return 0
130}