code wiki / _hdl_build / nx_mask_geom_register.nx
`nx_mask_geom_register.nx` source

1// nx_mask_geom_register.nx -- GOVERNED registration of Arc D2 mask geometry + DRC.
2// Engineer gate = REAL re-run of /tmp/nx_mask_geom_test.sov.elf (8/8). license_tier: ORIGINAL
3import "nx_cap_register.nx"
4import "nx_syscalls.nx"
5
6const MR_IDX: i64 = 223
7const MR_LAYER: i64 = 2   // GEN -- mask geometry synthesis (the chip-fab STL->G-code analog)
8const MR_NLAYERS: i64 = 6
9
10func mr_run_status(path: *u8) -> i64 {
11    let pid: i64 = sys_fork()
12    if pid == 0 {
13        let dn: i64 = sys_openat_wr("/dev/null" as *u8, 0x1a4)
14        if dn >= 0 { sys_dup3(dn, 1, 0); sys_dup3(dn, 2, 0) }
15        let argv: *i64 = sys_mmap(32) as *i64; argv[0] = path as i64; argv[1] = 0
16        let envp: *i64 = sys_mmap(16) as *i64; envp[0] = 0
17        sys_execve(path, argv, envp); sys_exit(127)
18    }
19    let st: *i64 = sys_mmap(16) as *i64
20    sys_wait4(pid, st, 0)
21    return st[0]
22}
23
24func main() -> i64 {
25    let elf: *u8 = "/tmp/nx_mask_geom_test.sov.elf" as *u8
26    let probe: i64 = sys_openat_rd(elf)
27    var present: i64 = 0
28    if probe >= 0 { present = 1; sys_close(probe) }
29    let raw: i64 = mr_run_status(elf)
30    var ran_no_signal: i64 = 0
31    if (raw % 128) == 0 { ran_no_signal = 1 }
32    var exit_ok: i64 = 0
33    if raw == 0 { exit_ok = 1 }
34    let eng: i64 = ig_engineer(present, present, ran_no_signal, exit_ok)
35    cr_w(1, "ENGINEER: mask-geom gate raw=" as *u8); cr_wn(1, raw); cr_w(1, " (0=8/8)\n" as *u8)
36    let council: i64 = ig_council(eng, 1, 1, 2)
37    let decision: i64 = ig_decision(eng, council, 1)
38    if decision != IG_INGEST { cr_w(1, "HELD\n" as *u8); sys_exit(1) }
39    if cr_can_register(MR_LAYER, 2, MR_NLAYERS, decision) != 1 { cr_w(1, "REFUSED\n" as *u8); sys_exit(1) }
40    let fd: i64 = sys_openat_append("/tmp/nishi_cap_registry.log" as *u8, 0x1a4)
41    cr_write_entry(fd, MR_IDX, MR_LAYER, "GEN MASK-GEOM (Arc D2, chip-fab STL->G-code analog) -- the team BUILDING what its assignment generator queued (D2). GDSII-class rectangular mask features on NANOMETER coords (nx_micron_geom); the S-class gate = DRC design-rule-check: mk_drc reports OK/THIN(min width)/CLOSE(min spacing)/OVERLAP, naming the offending feature(s) -- the real check every chip layout passes before a fab runs it. mk_critical_dimension + mk_makeable compose nx_metrology mt_can_make = the CPU-accuracy bridge (a 1um-CD layout is makeable by a 300nm SUBMICRON machine, NOT by 120um FDM). 8/8 KATs. Next rungs: arbitrary polygons + GDSII BINARY record emit" as *u8, 2)
42    sys_close(fd)
43    cr_w(1, "CAPREG idx=" as *u8); cr_wn(1, MR_IDX); cr_w(1, " REGISTERED\n" as *u8)
44    sys_exit(0)
45    return 0
46}
nx_mask_geom_register.nx source

`nx_mask_geom_register.nx` source
