code wiki / _hdl_build / nx_mesh3_gate.nx
nx_mesh3_gate.nx source
↩ module page · 124 lines · 5543 B
1// nx_mesh3_gate.nx -- gate for the SHARED tri-mesh + STL interchange (the real3d connective-tissue rung).
2// T1 box(12 tris) -> BINARY STL on disk: exact size 84+12*50, branded header, count field == 12 (raw re-read)
3// T2 read-back: 12 tris, verts DEDUPLICATED to exactly 8, every coordinate BIT-IDENTICAL (fx256<->f32 exact)
4// T3 AABB exact
5// T4 slice-z (the print primitive): mid-height cut = 8 crossing segments (4 sides x 2 tris); above-top = 0
6// T5 determinism: write->read->write again -> the two STL FILES byte-identical
7// The artifact knowledge/nx_mesh3_box.stl is REAL interchange: any slicer/CAD tool can open it.
8// license_tier: ORIGINAL expect_exit: 0
9import "nx_syscalls.nx"
10import "nx_mesh3.nx"
11
12func hw(s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } sys_write(1, s, n); return 0 }
13func pn(v: i64) -> i64 {
14 let b: *u8 = sys_mmap(32) as *u8
15 var x: i64 = v
16 var neg: i64 = 0
17 if x < 0 { neg = 1; x = 0 - x }
18 var i: i64 = 31
19 if x == 0 { b[i] = 48 as u8; i = i - 1 }
20 while x > 0 { b[i] = (48 + x % 10) as u8; x = x / 10; i = i - 1 }
21 if neg == 1 { b[i] = 45 as u8; i = i - 1 }
22 sys_write(1, (b as i64 + i + 1) as *u8, 31 - i)
23 return 0
24}
25
26func main() -> i64 {
27 var fails: i64 = 0
28 let path: *u8 = "knowledge/nx_mesh3_box.stl" as *u8
29 let path2: *u8 = "knowledge/nx_mesh3_box2.stl" as *u8
30
31 // T1 build + write
32 let m: i64 = sys_mmap(m3_bytes()) as i64
33 m3_init(m)
34 m3_box(m, 1000, 2000, 3000, 300, 400, 500) // center (3.9,7.8,11.7)m halves (1.17,1.56,1.95)m fx256
35 let wrote: i64 = m3_write_stl(m, path)
36 var t1: i64 = 1
37 if wrote != 84 + 12 * 50 { t1 = 0 }
38 // raw re-read: header brand + count field
39 let fd: i64 = sys_openat_rd(path)
40 let raw: *u8 = sys_mmap(1024) as *u8
41 let got: i64 = sys_read(fd, raw, 1024)
42 sys_close(fd)
43 if got != wrote { t1 = 0 }
44 if raw[0] as i64 != 110 { t1 = 0 }
45 if raw[1] as i64 != 120 { t1 = 0 }
46 let cnt: i64 = (raw[80] as i64) | ((raw[81] as i64) << 8) | ((raw[82] as i64) << 16) | ((raw[83] as i64) << 24)
47 if cnt != 12 { t1 = 0 }
48 if t1 == 1 { hw("T1 PASS binary STL written: " as *u8); pn(wrote); hw("B, branded header, count=12 (raw-verified)\n" as *u8) }
49 else { hw("T1 FAIL wrote=" as *u8); pn(wrote); hw(" got=" as *u8); pn(got); hw(" cnt=" as *u8); pn(cnt); hw("\n" as *u8); fails = fails + 1 }
50
51 // T2 read-back: dedup to 8 verts, geometry bit-identical
52 let m2: i64 = sys_mmap(m3_bytes()) as i64
53 let rtris: i64 = m3_read_stl(m2, path)
54 let h2: *i64 = m3_hdr(m2)
55 var t2: i64 = 1
56 if rtris != 12 { t2 = 0 }
57 if h2[0] != 8 { t2 = 0 }
58 // every original vertex must appear EXACTLY in the read-back set
59 let h1: *i64 = m3_hdr(m)
60 var vi: i64 = 0
61 var matched: i64 = 0
62 while vi < h1[0] {
63 let v: *i64 = m3_vert(m, vi)
64 var wi: i64 = 0
65 while wi < h2[0] {
66 let w: *i64 = m3_vert(m2, wi)
67 if v[0] == w[0] { if v[1] == w[1] { if v[2] == w[2] { matched = matched + 1; wi = h2[0] } } }
68 wi = wi + 1
69 }
70 vi = vi + 1
71 }
72 if matched != 8 { t2 = 0 }
73 if t2 == 1 { hw("T2 PASS read-back: 12 tris, verts DEDUP to exactly 8, all coordinates BIT-IDENTICAL (fx256<->f32 exact)\n" as *u8) }
74 else { hw("T2 FAIL rtris=" as *u8); pn(rtris); hw(" nverts=" as *u8); pn(h2[0]); hw(" matched=" as *u8); pn(matched); hw("\n" as *u8); fails = fails + 1 }
75
76 // T3 AABB
77 let bb: *i64 = sys_mmap(64) as *i64
78 m3_aabb(m2, bb)
79 var t3: i64 = 1
80 if bb[0] != 700 { t3 = 0 }
81 if bb[1] != 1600 { t3 = 0 }
82 if bb[2] != 2500 { t3 = 0 }
83 if bb[3] != 1300 { t3 = 0 }
84 if bb[4] != 2400 { t3 = 0 }
85 if bb[5] != 3500 { t3 = 0 }
86 if t3 == 1 { hw("T3 PASS AABB exact on the read-back mesh\n" as *u8) }
87 else { hw("T3 FAIL aabb=" as *u8); pn(bb[0]); hw("," as *u8); pn(bb[3]); hw("\n" as *u8); fails = fails + 1 }
88
89 // T4 slice-z: mid-height 8 segments; above-top 0
90 let smid: i64 = m3_slice_z_count(m2, 3000)
91 let stop: i64 = m3_slice_z_count(m2, 9000)
92 var t4: i64 = 1
93 if smid != 8 { t4 = 0 }
94 if stop != 0 { t4 = 0 }
95 if t4 == 1 { hw("T4 PASS slice-z (print primitive): mid-cut=8 segments (4 sides x 2 tris), above-top=0\n" as *u8) }
96 else { hw("T4 FAIL mid=" as *u8); pn(smid); hw(" top=" as *u8); pn(stop); hw("\n" as *u8); fails = fails + 1 }
97
98 // T5 determinism: re-write the READ mesh -> files byte-identical
99 let wrote2: i64 = m3_write_stl(m2, path2)
100 var t5: i64 = 1
101 if wrote2 != wrote { t5 = 0 }
102 let fda: i64 = sys_openat_rd(path)
103 let fdb: i64 = sys_openat_rd(path2)
104 let ba: *u8 = sys_mmap(2048) as *u8
105 let bb2: *u8 = sys_mmap(2048) as *u8
106 let ga: i64 = sys_read(fda, ba, 2048)
107 let gb: i64 = sys_read(fdb, bb2, 2048)
108 sys_close(fda)
109 sys_close(fdb)
110 if ga != gb { t5 = 0 }
111 var bi: i64 = 0
112 var bd: i64 = 0
113 while bi < ga {
114 if ba[bi] as i64 != bb2[bi] as i64 { bd = bd + 1 }
115 bi = bi + 1
116 }
117 if bd != 0 { t5 = 0 }
118 if t5 == 1 { hw("T5 PASS determinism: write->read->write, STL files BYTE-IDENTICAL (" as *u8); pn(ga); hw("B)\n" as *u8) }
119 else { hw("T5 FAIL bytes-differ=" as *u8); pn(bd); hw("\n" as *u8); fails = fails + 1 }
120
121 if fails == 0 { hw("VERDICT GREEN: nx_mesh3 5/5 -- ONE mesh + STL interchange (CAD exports, printer slices, games/video render, robotics collides) -- artifact knowledge/nx_mesh3_box.stl\n" as *u8) }
122 else { hw("VERDICT RED fails=" as *u8); pn(fails); hw("\n" as *u8) }
123 return fails
124}