nx_nofloat_moe_real_gate.nx source

1// nx_nofloat_moe_real_gate.nx -- MoE rung 3 (2026-07-15): REAL MoE WEIGHTS, LAZILY. Loads a real sparse-MoE 2// gguf (OLMoE-1B-7B: 64 experts, top-8, per-expert ff=1024, D=2048 -- the canonical small real MoE) and runs 3// ONE real MoE-FFN through our integer machinery with LAZY PER-SELECTED-EXPERT dequant -- the design the 4// operator's environment correction settled (dequant-once-everything is the WRONG shape for MoE; sparsity 5// means only K experts' weights are touched per token, so fetch exactly those). Composes the proven pieces: 6// nac_read_config (+ the MoE metadata keys), nx_gguf 3-D tensor info, dequant_row / dequant_to_q16 windows, 7// mm_out_in / fx_exp / silu / qmul. HONEST SCOPE: this rung proves REAL-WEIGHT ROUTING + LAZY FETCH + THE 8// MIX MECHANISM on blk.0 -- NOT a faithful OLMoE model output (full arch = QK-norm etc., a later rung). 9// T1 MoE METADATA read from the model itself: expert_count=64, expert_used_count=8 (olmoe.* keys) 10// T2 3-D expert tensors located, dims EXACT (gate/up [D,ff,E]; down [ff,D,E]; router [D,E] 2-D) 11// T3 LAZY-SLICE LIAR-KILLER: bulk expert-slice dequant (type-aware block offset) == per-row dequant_row 12// on sampled rows x sampled experts x gate+down, EXACT (0 mismatches) -- kills offset-math bugs 13// T4 REAL ROUTING: top-8 = 8 distinct ids; deterministic repeat; a second input selects a DIFFERENT set 14// (the real router discriminates -- the neg-control against constant routing) 15// T5 REAL MIX: K experts lazily fetched (counter == 8), output dense-nonzero, byte-identical repeat 16// Requires /home/elderwesto/nx_stage/nx_moe_model.gguf. ~4.4GB read; slices ~400MB. Return from main. 17// No hw writes (Rule 26). expect_exit: 0 license_tier: ORIGINAL 18import "nx_syscalls.nx" 19import "nx_tier.nx" 20import "nx_le.nx" 21import "nx_tensor.nx" 22import "nx_gguf.nx" 23import "nx_gguf_load.nx" 24import "nx_gguf_meta.nx" 25import "nx_nofloat_llm.nx" 26import "nx_nofloat_arch.nx" 27import "nx_gate_verdict.nx" 28 29func mr_w(s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } sys_write(1, s, n); return 0 } 30func mr_n(v: i64) -> i64 { 31 var m: i64 = v 32 if m < 0 { mr_w("-" as *u8); m = 0 - m } 33 let t: *u8 = sys_mmap(24) 34 var k: i64 = 0 35 if m == 0 { t[0] = 48 as u8; k = 1 } 36 while m > 0 { t[k] = (48 + (m % 10)) as u8; m = m / 10; k = k + 1 } 37 let o: *u8 = sys_mmap(24) 38 var i: i64 = 0 39 while i < k { o[i] = t[k - 1 - i]; i = i + 1 } 40 sys_write(1, o, k) 41 return 0 42} 43func mr_slen(s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } return n } 44func mr_det(i: i64) -> i64 { return ((i * 2654435761) % 8191) - 4095 } 45 46// byte offset of value index `voff` inside a quantized tensor blob -- rides the CANONICAL type-stride 47// table (nf_type_stride, debt-eaten 2026-07-15: full mainstream family, -1 on unknown). Valid only when 48// voff is block-aligned (expert slices are: ff*D is a multiple of 256 for OLMoE). 49func mr_val_byteoff(ty: i64, voff: i64) -> i64 { 50 let vb: *i64 = sys_mmap(16) as *i64 51 if nf_type_stride(ty, vb) != 0 { return 0 - 1 } 52 return (voff / vb[0]) * vb[1] 53} 54 55func main() -> i64 { 56 mr_w("=== NX-NOFLOAT-MOE-REAL -- real sparse-MoE weights (OLMoE 64-expert top-8), lazy per-expert fetch ===\n" as *u8) 57 let path: *u8 = "/home/elderwesto/nx_stage/nx_moe_model.gguf" as *u8 58 let len_out: *i64 = sys_mmap(8) as *i64 59 len_out[0] = 0 60 mr_w("[load] mapping gguf (zero-copy, read-only)...\n" as *u8) 61 let t0: i64 = sys_now_ms() 62 let buf: *u8 = sys_map_file(path, len_out) 63 let t1: i64 = sys_now_ms() 64 if (buf as i64) == 0 { mr_w("MODEL ABSENT\n" as *u8); return 1 } 65 mr_w("[load] mapped in " as *u8); mr_n(t1 - t0); mr_w(" ms (only touched pages will become resident)\n" as *u8) 66 let hdr: *NxGgufHeader = sys_mmap(NX_GGUF_HDR_BYTES) as *NxGgufHeader 67 if nx_gguf_parse(buf, len_out[0], hdr) != NX_GGUF_OK { mr_w("PARSE FAIL\n" as *u8); return 1 } 68 let hloc: *NxGgufHeader = hdr 69 mr_w("[load] bytes=" as *u8); mr_n(len_out[0]); mr_w(" tensors=" as *u8); mr_n(hloc.tensor_count); mr_w("\n" as *u8) 70 71 // arch config + MoE keys from METADATA 72 let cfg: *i64 = sys_mmap(16*8) as *i64 73 let arch: *u8 = sys_mmap(48) 74 if nac_read_config(buf, len_out[0], hdr, cfg, arch) != 0 { mr_w("ARCH CONFIG FAIL\n" as *u8); return 1 } 75 let D: i64 = cfg[0] 76 let FF: i64 = cfg[7] 77 let alen: i64 = mr_slen(arch) 78 let EC: i64 = nac_u32(buf, len_out[0], hdr, arch, alen, ".expert_count" as *u8) 79 let EU: i64 = nac_u32(buf, len_out[0], hdr, arch, alen, ".expert_used_count" as *u8) 80 mr_w("[arch] " as *u8); mr_w(arch); mr_w(" D=" as *u8); mr_n(D); mr_w(" ff=" as *u8); mr_n(FF) 81 mr_w(" experts=" as *u8); mr_n(EC); mr_w(" used=" as *u8); mr_n(EU); mr_w("\n" as *u8) 82 83 // locate blk.0 router + 3-D expert tensors 84 let nR: *u8 = "blk.0.ffn_gate_inp.weight" as *u8 85 let nG: *u8 = "blk.0.ffn_gate_exps.weight" as *u8 86 let nU: *u8 = "blk.0.ffn_up_exps.weight" as *u8 87 let nD: *u8 = "blk.0.ffn_down_exps.weight" as *u8 88 let iR: nx_int = nx_gguf_find_tensor(hdr, nR, mr_slen(nR)) 89 let iG: nx_int = nx_gguf_find_tensor(hdr, nG, mr_slen(nG)) 90 let iU: nx_int = nx_gguf_find_tensor(hdr, nU, mr_slen(nU)) 91 let iD: nx_int = nx_gguf_find_tensor(hdr, nD, mr_slen(nD)) 92 if iR < 0 { mr_w("router tensor ABSENT\n" as *u8); return 1 } 93 if iG < 0 { mr_w("gate_exps ABSENT\n" as *u8); return 1 } 94 if iU < 0 { mr_w("up_exps ABSENT\n" as *u8); return 1 } 95 if iD < 0 { mr_w("down_exps ABSENT\n" as *u8); return 1 } 96 let tR: *NxGgufTensorInfo = nx_gguf_tensor_at(hloc, iR) 97 let tG: *NxGgufTensorInfo = nx_gguf_tensor_at(hloc, iG) 98 let tU: *NxGgufTensorInfo = nx_gguf_tensor_at(hloc, iU) 99 let tD: *NxGgufTensorInfo = nx_gguf_tensor_at(hloc, iD) 100 let bR: i64 = hloc.data_off + tR.offset 101 let bG: i64 = hloc.data_off + tG.offset 102 let bU: i64 = hloc.data_off + tU.offset 103 let bD: i64 = hloc.data_off + tD.offset 104 mr_w("[tensors] gate_exps dims=" as *u8); mr_n(tG.dim_0); mr_w("x" as *u8); mr_n(tG.dim_1); mr_w("x" as *u8); mr_n(tG.dim_2) 105 mr_w(" ty=" as *u8); mr_n(tG.ggml_type) 106 mr_w(" | down_exps dims=" as *u8); mr_n(tD.dim_0); mr_w("x" as *u8); mr_n(tD.dim_1); mr_w("x" as *u8); mr_n(tD.dim_2) 107 mr_w(" ty=" as *u8); mr_n(tD.ggml_type); mr_w("\n" as *u8) 108 109 // T1 metadata teeth 110 var pass: i64 = 0 111 var ttl: i64 = 0 112 ttl = ttl + 1 113 var ok1: i64 = 0 114 if EC == 64 { if EU == 8 { ok1 = 1 } } 115 mr_w(" T1 MoE metadata from the model (expert_count=64, expert_used_count=8): " as *u8) 116 if ok1 == 1 { pass = pass + 1; mr_w("PASS\n" as *u8) } else { mr_w("FAIL\n" as *u8) } 117 118 // T2 dims teeth: gate/up [D,ff,E]; down [ff,D,E]; router 2-D [D,E] 119 ttl = ttl + 1 120 var ok2: i64 = 1 121 if tG.n_dims != 3 { ok2 = 0 } 122 if tG.dim_0 != D { ok2 = 0 } 123 if tG.dim_1 != FF { ok2 = 0 } 124 if tG.dim_2 != EC { ok2 = 0 } 125 if tU.n_dims != 3 { ok2 = 0 } 126 if tU.dim_0 != D { ok2 = 0 } 127 if tD.n_dims != 3 { ok2 = 0 } 128 if tD.dim_0 != FF { ok2 = 0 } 129 if tD.dim_1 != D { ok2 = 0 } 130 if tR.n_dims != 2 { ok2 = 0 } 131 if tR.dim_0 != D { ok2 = 0 } 132 if tR.dim_1 != EC { ok2 = 0 } 133 mr_w(" T2 tensor shapes exact (3-D experts as 2-D row views): " as *u8) 134 if ok2 == 1 { pass = pass + 1; mr_w("PASS\n" as *u8) } else { mr_w("FAIL\n" as *u8) } 135 136 // T3 LAZY-SLICE LIAR-KILLER: bulk expert-slice dequant == per-row dequant_row, sampled 137 let tmp: *i64 = sys_mmap(64*256*8) as *i64 138 let rowbuf: *i64 = sys_mmap(D*8) as *i64 139 let slice: *i64 = sys_mmap(FF*D*8) as *i64 140 var t3_mism: i64 = 0 141 var se: i64 = 0 142 while se < 2 { 143 var e: i64 = 3 144 if se == 1 { e = 41 } 145 // gate slice: rows [e*FF, (e+1)*FF) of the [EC*FF, D] 2-D view 146 let voffG: i64 = e * FF * D 147 let boffG: i64 = mr_val_byteoff(tG.ggml_type, voffG) 148 if boffG < 0 { t3_mism = t3_mism + 1000000 } else { 149 dequant_to_q16(buf, bG + boffG, tG.ggml_type, FF*D, slice) 150 var sr: i64 = 0 151 while sr < 4 { 152 var r2: i64 = 0 153 if sr == 1 { r2 = 1 } 154 if sr == 2 { r2 = FF/2 } 155 if sr == 3 { r2 = FF - 1 } 156 dequant_row(buf, bG, tG.ggml_type, e*FF + r2, D, rowbuf, tmp) 157 var d: i64 = 0 158 while d < D { if rowbuf[d] != slice[r2*D + d] { t3_mism = t3_mism + 1 } d = d + 1 } 159 sr = sr + 1 160 } 161 } 162 // down slice: rows [e*D, (e+1)*D) of the [EC*D, FF] 2-D view 163 let voffD: i64 = e * D * FF 164 let boffD: i64 = mr_val_byteoff(tD.ggml_type, voffD) 165 if boffD < 0 { t3_mism = t3_mism + 1000000 } else { 166 dequant_to_q16(buf, bD + boffD, tD.ggml_type, D*FF, slice) 167 var sr2: i64 = 0 168 while sr2 < 4 { 169 var r3: i64 = 0 170 if sr2 == 1 { r3 = 1 } 171 if sr2 == 2 { r3 = D/2 } 172 if sr2 == 3 { r3 = D - 1 } 173 dequant_row(buf, bD, tD.ggml_type, e*D + r3, FF, rowbuf, tmp) 174 var f: i64 = 0 175 while f < FF { if rowbuf[f] != slice[r3*FF + f] { t3_mism = t3_mism + 1 } f = f + 1 } 176 sr2 = sr2 + 1 177 } 178 } 179 se = se + 1 180 } 181 ttl = ttl + 1 182 let ok3: i64 = (t3_mism == 0) as i64 183 mr_w(" T3 lazy-slice dequant == per-row window, sampled rows x 2 experts x gate+down (mism " as *u8); mr_n(t3_mism); mr_w("): " as *u8) 184 if ok3 == 1 { pass = pass + 1; mr_w("PASS\n" as *u8) } else { mr_w("FAIL\n" as *u8) } 185 186 // T4 REAL ROUTING on two inputs 187 let Wr: *i64 = sys_mmap(EC*D*8) as *i64 188 dequant_to_q16(buf, bR, tR.ggml_type, EC*D, Wr) 189 let x1: *i64 = sys_mmap(D*8) as *i64 190 let x2: *i64 = sys_mmap(D*8) as *i64 191 var i: i64 = 0 192 while i < D { x1[i] = mr_det(i + 7); x2[i] = mr_det(i*3 + 501); i = i + 1 } 193 let r: *i64 = sys_mmap(EC*8) as *i64 194 let sel1: *i64 = sys_mmap(EU*8) as *i64 195 let sel2: *i64 = sys_mmap(EU*8) as *i64 196 let selr: *i64 = sys_mmap(EU*8) as *i64 197 var pi: i64 = 0 198 while pi < 3 { 199 var xp: *i64 = x1 200 var sp: *i64 = sel1 201 if pi == 1 { xp = x2; sp = sel2 } 202 if pi == 2 { xp = x1; sp = selr } 203 mm_out_in(xp, Wr, r, 1, D, EC, 0) 204 var ki: i64 = 0 205 while ki < EU { 206 var best: i64 = 0 - 1 207 var bestv: i64 = 0 208 var e2: i64 = 0 209 while e2 < EC { 210 var taken: i64 = 0 211 var q: i64 = 0 212 while q < ki { if sp[q] == e2 { taken = 1 } q = q + 1 } 213 if taken == 0 { if best < 0 { best = e2; bestv = r[e2] } else { if r[e2] > bestv { best = e2; bestv = r[e2] } } } 214 e2 = e2 + 1 215 } 216 sp[ki] = best 217 ki = ki + 1 218 } 219 pi = pi + 1 220 } 221 mr_w(" [route x1] experts:" as *u8) 222 i = 0 223 while i < EU { mr_w(" " as *u8); mr_n(sel1[i]); i = i + 1 } 224 mr_w("\n [route x2] experts:" as *u8) 225 i = 0 226 while i < EU { mr_w(" " as *u8); mr_n(sel2[i]); i = i + 1 } 227 mr_w("\n" as *u8) 228 var distinct1: i64 = 1 229 i = 0 230 while i < EU { var j2: i64 = i + 1; while j2 < EU { if sel1[i] == sel1[j2] { distinct1 = 0 } j2 = j2 + 1 } i = i + 1 } 231 var det_ok: i64 = 1 232 i = 0 233 while i < EU { if sel1[i] != selr[i] { det_ok = 0 } i = i + 1 } 234 var differs: i64 = 0 235 i = 0 236 while i < EU { var found: i64 = 0; var j3: i64 = 0; while j3 < EU { if sel2[j3] == sel1[i] { found = 1 } j3 = j3 + 1 } if found == 0 { differs = 1 } i = i + 1 } 237 ttl = ttl + 1 238 var ok4: i64 = distinct1 & det_ok 239 ok4 = ok4 & differs 240 mr_w(" T4 real routing: 8 distinct, deterministic repeat, second input differs: " as *u8) 241 if ok4 == 1 { pass = pass + 1; mr_w("PASS\n" as *u8) } else { mr_w("FAIL\n" as *u8) } 242 243 // T5 REAL MIX: lazily fetch the EU selected experts' gate/up/down slices, SwiGLU mix (softmax over selected) 244 let gs: *i64 = sys_mmap(FF*D*8) as *i64 245 let us: *i64 = sys_mmap(FF*D*8) as *i64 246 let ds: *i64 = sys_mmap(D*FF*8) as *i64 247 let g: *i64 = sys_mmap(FF*8) as *i64 248 let u: *i64 = sys_mmap(FF*8) as *i64 249 let h: *i64 = sys_mmap(FF*8) as *i64 250 let eo: *i64 = sys_mmap(D*8) as *i64 251 let out1: *i64 = sys_mmap(D*8) as *i64 252 let out2: *i64 = sys_mmap(D*8) as *i64 253 let wgt: *i64 = sys_mmap(EU*8) as *i64 254 var fetched: i64 = 0 255 var rep: i64 = 0 256 while rep < 2 { 257 var outp: *i64 = out1 258 if rep == 1 { outp = out2 } 259 mm_out_in(x1, Wr, r, 1, D, EC, 0) 260 var m: i64 = r[sel1[0]] 261 i = 1 262 while i < EU { if r[sel1[i]] > m { m = r[sel1[i]] } i = i + 1 } 263 var sum: i64 = 0 264 i = 0 265 while i < EU { let ev: i64 = fx_exp(r[sel1[i]] - m); wgt[i] = ev; sum = sum + ev; i = i + 1 } 266 if sum < 1 { sum = 1 } 267 i = 0 268 while i < EU { wgt[i] = (wgt[i] << 16) / sum; i = i + 1 } 269 var d3: i64 = 0 270 while d3 < D { outp[d3] = 0; d3 = d3 + 1 } 271 i = 0 272 while i < EU { 273 let e3: i64 = sel1[i] 274 dequant_to_q16(buf, bG + mr_val_byteoff(tG.ggml_type, e3*FF*D), tG.ggml_type, FF*D, gs) 275 dequant_to_q16(buf, bU + mr_val_byteoff(tU.ggml_type, e3*FF*D), tU.ggml_type, FF*D, us) 276 dequant_to_q16(buf, bD + mr_val_byteoff(tD.ggml_type, e3*D*FF), tD.ggml_type, D*FF, ds) 277 if rep == 0 { fetched = fetched + 1 } 278 mm_out_in(x1, gs, g, 1, D, FF, 0) 279 mm_out_in(x1, us, u, 1, D, FF, 0) 280 var j4: i64 = 0 281 while j4 < FF { h[j4] = qmul(silu(g[j4]), u[j4]); j4 = j4 + 1 } 282 mm_out_in(h, ds, eo, 1, FF, D, 0) 283 d3 = 0 284 while d3 < D { outp[d3] = outp[d3] + qmul(wgt[i], eo[d3]); d3 = d3 + 1 } 285 i = i + 1 286 } 287 rep = rep + 1 288 } 289 var nz: i64 = 0 290 var rep_mism: i64 = 0 291 i = 0 292 while i < D { if out1[i] != 0 { nz = nz + 1 } if out1[i] != out2[i] { rep_mism = rep_mism + 1 } i = i + 1 } 293 ttl = ttl + 1 294 var ok5: i64 = ((fetched == EU) as i64) & ((nz >= D/2) as i64) 295 ok5 = ok5 & ((rep_mism == 0) as i64) 296 mr_w(" T5 real mix: fetched " as *u8); mr_n(fetched); mr_w("/" as *u8); mr_n(EU) 297 mr_w(" experts lazily, nz " as *u8); mr_n(nz); mr_w("/" as *u8); mr_n(D) 298 mr_w(", repeat mism " as *u8); mr_n(rep_mism); mr_w(": " as *u8) 299 if ok5 == 1 { pass = pass + 1; mr_w("PASS\n" as *u8) } else { mr_w("FAIL\n" as *u8) } 300 301 mr_w("NX-NOFLOAT-MOE-REAL-GATE passed " as *u8); mr_n(pass); mr_w("/" as *u8); mr_n(ttl) 302 // MIGRATED onto nx_gate_verdict by nx_gate_dry_apply (D001, minimal form): every check 303 // row above is untouched, so the PASS/FAIL vector cannot change; only the hand-rolled 304 // verdict emission is replaced by the ONE shared base class. Proven by nx_gate_migrate verify. 305 let ctr__dry: *i64 = gv_ctr() 306 ctr__dry[0] = pass 307 ctr__dry[1] = ttl 308 let rc__dry: i64 = gv_verdict("NOFLOAT-MOE-REAL-GATE" as *u8, ctr__dry, "real 64-expert MoE routes + lazily fetches + mixes in deterministic integer)" as *u8) 309 sys_exit(rc__dry) 310 return rc__dry 311}