`nx_nv_gate.nx` source

1// nx_nv_gate.nx -- gate for the native-Linux NVIDIA executor (nx_nv). Verifies the LOCALLY-verifiable core
2// bit-exact (the GPFIFO entry encoder, real hardware format per tinygrad ops_nv.py) + reports the device-iface
3// status (on WSL2 the /dev/nvidia* nodes are ABSENT -> the EXECUTE is honestly CLOUD-PENDING, run on a rented
4// native-Linux GPU instance = BM-GPU-6). No hw writes (Rule 26). expect_exit: 0  license_tier: ORIGINAL
5import "nx_syscalls.nx"
6import "nx_nv.nx"
7
8func bp(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 }
9func bx(v: i64) -> i64 { bp("0x" as *u8); let bb:*u8=sys_mmap(20); var k:i64=0; var m:i64=v; if m==0{bb[0]=48 as u8;k=1} while m>0{ let d:i64=m&15; if d<10{bb[k]=(48+d) as u8}else{bb[k]=(87+d) as u8}; m=(m>>4); k=k+1 } var i:i64=0; let o:*u8=sys_mmap(20); while i<k{o[i]=bb[k-1-i];i=i+1} sys_write(1,o,k); return 0 }
10func bd(v: i64) -> i64 { let p: *u8=sys_mmap(1); p[0]=(48+v) as u8; sys_write(1,p,1); return 0 }
11
12func chk(name: *u8, got: i64, ref: i64, st: *i64) -> i64 {
13    bp("  gpfifo_entry " as *u8); bp(name); bp(" -> " as *u8); bx(got)
14    if got==ref { bp("  == hw-format ref  PASS\n" as *u8); st[0]=st[0]+1; return 0 }
15    bp("  != ref " as *u8); bx(ref); bp("  FAIL\n" as *u8); return 0
16}
17
18func main() -> i64 {
19    bp("=== native-Linux NVIDIA executor (nx_nv) -- GPFIFO entry encoder bit-exact + device-iface routing ===\n" as *u8)
20
21    // device-iface: on WSL2 absent -> EXECUTE is cloud-pending; on a native/cloud instance these open.
22    let ctl: i64 = nv_open_ctl()
23    var have_ctl: i64 = 0
24    if ctl >= 0 { have_ctl = 1; sys_close(ctl) }
25    bp("  /dev/nvidiactl present=" as *u8); bd(have_ctl)
26    if have_ctl == 1 { bp("  -> native-Linux: BM-GPU-6 EXECUTE runnable HERE\n" as *u8) } else { bp("  -> WSL2/no-native: EXECUTE cloud-pending (rent a native-Linux GPU instance)\n" as *u8) }
27
28    // ---- locally-verifiable: the GPFIFO entry encoder (real hardware format, tinygrad-confirmed) ----
29    let st: *i64 = sys_mmap(8); st[0]=0
30    chk("va=0x32c000 len=6 " as *u8, nv_gpfifo_entry(0x32c000, 6), 0x1a000032c000, st)
31    chk("va=0x33c000 len=4 " as *u8, nv_gpfifo_entry(0x33c000, 4), 0x12000033c000, st)
32    chk("va=0x400000 len=2 " as *u8, nv_gpfifo_entry(0x400000, 2), 0xa0000400000,  st)
33    chk("va=0x500000 len=1 " as *u8, nv_gpfifo_entry(0x500000, 1), 0x60000500000,  st)
34    // alignment: a non-4-aligned VA must have its low 2 bits cleared (== the aligned entry)
35    chk("va=0x32c001 align " as *u8, nv_gpfifo_entry(0x32c001, 6), 0x1a000032c000, st)
36
37    // negative control: distinct VA -> distinct entry (proves the encoder reads the address)
38    var neg_ok: i64 = 0
39    if nv_gpfifo_entry(0x32c000, 6) != nv_gpfifo_entry(0x33c000, 6) { neg_ok = 1 }
40    bp("  NEG distinct-va distinct-entry: " as *u8); if neg_ok==1 { bp("PASS\n" as *u8) } else { bp("FAIL\n" as *u8) }
41
42    let pass: i64 = st[0]
43    bp("NV-EXECUTOR-GATE entry_encoder " as *u8); bd(pass); bp("/5  neg=" as *u8); bd(neg_ok); bp(" doorbell_off=" as *u8); bx(0x90); bp(" execute=" as *u8); if have_ctl==1 { bp("native-runnable" as *u8) } else { bp("CLOUD-PENDING" as *u8) }; bp("\n" as *u8)
44    if pass==5 { if neg_ok==1 { bp("verdict=GREEN (GPFIFO entry encoder bit-exact [tinygrad-confirmed format]; doorbell offset 0x90; full RM object tree + real EXECUTE = cloud-pending on native-Linux silicon)\n" as *u8); sys_exit(0); return 0 } }
45    bp("verdict=RED\n" as *u8); sys_exit(1); return 1
46}
nx_nv_gate.nx source

`nx_nv_gate.nx` source
