nx_pagefault_emit.nx source

1// nx_pagefault_emit.nx -- PAGE-FAULT TRAP test (Sv39 paging completion rung). 2// 3// Table-computes a bare-metal rv64 image that proves the CPU raises a LOAD-PAGE-FAULT trap on an 4// unmapped virtual address and vectors to the handler (mtvec) -- the foundation of demand paging / 5// memory protection. Sequence (satp = Sv39 throughout after it is set): 6// 1. install mtvec = &handler (physical; fetch is untranslated so the handler runs physically) 7// 2. lay a valid gigapage PTE + a sentinel; csrrw satp (Sv39 ON) 8// 3. load the MAPPED VA 0xC0009000 -> sentinel -> verify -> emit "OK" 9// 4. load the UNMAPPED VA 0x00009000 -> the walk faults -> the CPU takes a load-page-fault trap 10// -> PC = mtvec -> the handler emits "PF" and halts. (If the fault did NOT fire, control 11// falls through to emit "N" -> the gate sees no "PF" = RED.) 12// Success transcript = "OKPF". The handler's UART/finisher writes hit device MMIO (xlate-exempt), 13// so it works with paging on. Zero hand-written machine code; two-pass forward-ref resolution. 14// nx_pagefault_emit -> runtime/_hdl_build/_pagefault_virt.bin + .gold 15// Sovereign, no gcc/.sh. license_tier: ORIGINAL 16import "nx_syscalls.nx" 17const PF_MAGIC_8192: i64 = 8192 18 19const PF_OUT: *u8 = "runtime/_hdl_build/_pagefault_virt.bin" 20const PF_GOLD: *u8 = "runtime/_hdl_build/_pagefault_virt.bin.gold" 21const PF_LOG: *u8 = "knowledge/status/paging.log" 22 23const PF_UART: i64 = 0x10000000 24const PF_FIN: i64 = 0x100000 25const PF_PASS: i64 = 0x5555 26const PF_MEM_BASE: i64 = 0x80000000 27const PF_CSR_SATP: i64 = 0x180 28const PF_CSR_MTVEC: i64 = 0x305 29const PF_CSR_MSTATUS: i64 = 0x300 30const PF_CSR_MEPC: i64 = 0x341 31const PF_MRET: i64 = 0x30200073 32const PF_MPP_S: i64 = 0x800 33 34const RV_X0: i64 = 0 35const RV_T0: i64 = 5 36const RV_T1: i64 = 6 37const RV_T2: i64 = 7 38const RV_T3: i64 = 28 39const RV_T4: i64 = 29 40const RV_T5: i64 = 30 41 42const PF_PTE_ADDR: i64 = 0x80008000 43const PF_PTE_OFF: i64 = 0x18 44const PF_PTE_VAL: i64 = 0x20000007 45const PF_SENT_PA: i64 = 0x80009000 46const PF_SENT_VAL: i64 = 0x5ECA1234 47const PF_VA_MAP: i64 = 0xC0009000 48const PF_VA_UNMAP: i64 = 0x00009000 49const PF_SATP_PPN: i64 = 0x80008 50const PF_SV39: i64 = 8 51 52func pf_lui(rd: i64, imm20: i64) -> i64 { return ((imm20 & 0xFFFFF) << 12) | (rd << 7) | 0x37 } 53func pf_addi(rd: i64, rs1: i64, imm: i64) -> i64 { return ((imm & 0xFFF) << 20) | (rs1 << 15) | (rd << 7) | 0x13 } 54func pf_load(rd: i64, rs1: i64, f3: i64, imm: i64) -> i64 { return ((imm & 0xFFF) << 20) | (rs1 << 15) | (f3 << 12) | (rd << 7) | 0x03 } 55func pf_store(rs2: i64, rs1: i64, f3: i64, imm: i64) -> i64 { 56 let hi: i64 = ((imm >> 5) & 0x7f) << 25 57 let lo: i64 = (imm & 0x1f) << 7 58 return hi | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | lo | 0x23 59} 60func pf_branch(rs1: i64, rs2: i64, f3: i64, imm: i64) -> i64 { 61 let b12: i64 = ((imm >> 12) & 0x1) << 31 62 let b11: i64 = ((imm >> 11) & 0x1) << 7 63 let b10_5: i64 = ((imm >> 5) & 0x3f) << 25 64 let b4_1: i64 = ((imm >> 1) & 0xf) << 8 65 return b12 | b10_5 | (rs2 << 20) | (rs1 << 15) | (f3 << 12) | b4_1 | b11 | 0x63 66} 67func pf_jal(rd: i64, imm: i64) -> i64 { 68 let b20: i64 = ((imm >> 20) & 0x1) << 31 69 let b19_12: i64 = ((imm >> 12) & 0xff) << 12 70 let b11: i64 = ((imm >> 11) & 0x1) << 20 71 let b10_1: i64 = ((imm >> 1) & 0x3ff) << 21 72 return b20 | b10_1 | b11 | b19_12 | (rd << 7) | 0x6f 73} 74func pf_slli(rd: i64, rs1: i64, shamt: i64) -> i64 { return ((shamt & 0x3f) << 20) | (rs1 << 15) | (1 << 12) | (rd << 7) | 0x13 } 75func pf_srli(rd: i64, rs1: i64, shamt: i64) -> i64 { return ((shamt & 0x3f) << 20) | (rs1 << 15) | (5 << 12) | (rd << 7) | 0x13 } 76func pf_or(rd: i64, rs1: i64, rs2: i64) -> i64 { return (rs2 << 20) | (rs1 << 15) | (6 << 12) | (rd << 7) | 0x33 } 77func pf_csrrw(rd: i64, csr: i64, rs1: i64) -> i64 { return ((csr & 0xfff) << 20) | (rs1 << 15) | (1 << 12) | (rd << 7) | 0x73 } 78func pf_w32(buf: *u8, off: i64, w: i64) -> i64 { buf[off]=(w&0xff) as u8; buf[off+1]=((w>>8)&0xff) as u8; buf[off+2]=((w>>16)&0xff) as u8; buf[off+3]=((w>>24)&0xff) as u8; return off+4 } 79func pf_li32(buf: *u8, off: i64, rd: i64, val: i64) -> i64 { 80 var hi: i64 = (val >> 12) & 0xFFFFF 81 var lo: i64 = val & 0xFFF 82 if lo >= 0x800 { lo = lo - 0x1000; hi = (hi + 1) & 0xFFFFF } 83 var o: i64 = pf_w32(buf, off, pf_lui(rd, hi)) 84 o = pf_w32(buf, o, pf_addi(rd, rd, lo)) 85 return o 86} 87func pf_li32u(buf: *u8, off: i64, rd: i64, val: i64) -> i64 { 88 var o: i64 = pf_li32(buf, off, rd, val) 89 o = pf_w32(buf, o, pf_slli(rd, rd, 32)) 90 o = pf_w32(buf, o, pf_srli(rd, rd, 32)) 91 return o 92} 93func pf_emit_str(buf: *u8, off: i64, s: *u8, n: i64) -> i64 { 94 var o: i64 = off 95 var i: i64 = 0 96 while i < n { o = pf_w32(buf, o, pf_addi(RV_T1, RV_X0, s[i] as i64)); o = pf_w32(buf, o, pf_store(RV_T1, RV_T0, 0, 0)); i = i + 1 } 97 return o 98} 99func pf_p(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } 100func pf_fn(fd: i64, v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m}; let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48;k=1}; while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1}; var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1}; sys_write(fd,bb,k); return 0 } 101 102// pos_out[0]=FAIL, [1]=HALT, [2]=HANDLER offsets. handler_phys = PF_MEM_BASE + handler_off. 103func pf_emit_image(buf: *u8, fail_off: i64, halt_off: i64, handler_off: i64, pos_out: *i64, unmap_va: i64, cont_off: i64) -> i64 { 104 var o: i64 = 0 105 o = pf_w32(buf, o, pf_lui(RV_T0, PF_UART >> 12)) // t0 = UART 106 // install mtvec = &handler (physical) 107 o = pf_li32u(buf, o, RV_T1, PF_MEM_BASE + handler_off) 108 o = pf_w32(buf, o, pf_csrrw(RV_X0, PF_CSR_MTVEC, RV_T1)) // mtvec = handler (M-CSR; set in M-mode) 109 // enter S-mode (paging applies only in S/U): mepc = &cont; mstatus.MPP = S; mret 110 o = pf_li32u(buf, o, RV_T1, PF_MEM_BASE + cont_off) 111 o = pf_w32(buf, o, pf_csrrw(RV_X0, PF_CSR_MEPC, RV_T1)) 112 o = pf_li32(buf, o, RV_T1, PF_MPP_S) 113 o = pf_w32(buf, o, pf_csrrw(RV_X0, PF_CSR_MSTATUS, RV_T1)) 114 o = pf_w32(buf, o, PF_MRET) 115 pos_out[3] = o // cont: runs in S-mode 116 // lay PTEs + sentinel. root[VPN2=2] (offset 0x10) = always-valid gigapage identity map for the 117 // kernel text (VA 0x80000000.. -> PA 0x80000000..) so the S-mode code can be FETCHED under Sv39; 118 // the data leaf root[VPN2=3] (offset 0x18) maps VA 0xC0000000.. for the load test. 119 o = pf_li32u(buf, o, RV_T5, PF_PTE_ADDR) 120 o = pf_li32(buf, o, RV_T1, 0x2000000F) // identity code-map gigapage (PPN 0x80000, V|R|W|X -- X required to FETCH under perm enforcement) 121 o = pf_w32(buf, o, pf_store(RV_T1, RV_T5, 2, 0x10)) // sw code-map, 0x10(t5) = root[VPN2=2] 122 o = pf_li32(buf, o, RV_T1, PF_PTE_VAL) 123 o = pf_w32(buf, o, pf_store(RV_T1, RV_T5, 2, PF_PTE_OFF)) 124 o = pf_li32u(buf, o, RV_T5, PF_SENT_PA) 125 o = pf_li32(buf, o, RV_T1, PF_SENT_VAL) 126 o = pf_w32(buf, o, pf_store(RV_T1, RV_T5, 2, 0)) 127 // satp = Sv39|PPN 128 o = pf_li32(buf, o, RV_T1, PF_SATP_PPN) 129 o = pf_w32(buf, o, pf_addi(RV_T2, RV_X0, PF_SV39)) 130 o = pf_w32(buf, o, pf_slli(RV_T2, RV_T2, 60)) 131 o = pf_w32(buf, o, pf_or(RV_T1, RV_T1, RV_T2)) 132 o = pf_w32(buf, o, pf_csrrw(RV_X0, PF_CSR_SATP, RV_T1)) 133 // mapped load + verify -> "OK" 134 o = pf_li32u(buf, o, RV_T5, PF_VA_MAP) 135 o = pf_w32(buf, o, pf_load(RV_T3, RV_T5, 2, 0)) 136 o = pf_li32(buf, o, RV_T4, PF_SENT_VAL) 137 let pcb: i64 = o 138 o = pf_w32(buf, o, pf_branch(RV_T3, RV_T4, 1, fail_off - pcb)) // bne -> FAIL 139 o = pf_emit_str(buf, o, "OK" as *u8, 2) 140 // second load -> page fault -> handler (mtvec). unmap_va is the unmapped VA by default; the 141 // gate's control passes a MAPPED VA instead (no fault -> falls through to "N" -> no "PF"). 142 o = pf_li32u(buf, o, RV_T5, unmap_va) 143 o = pf_w32(buf, o, pf_load(RV_T3, RV_T5, 2, 0)) // FAULTS -> PC=mtvec 144 // (no-fault bug path) emit "N" then halt 145 o = pf_emit_str(buf, o, "N" as *u8, 1) 146 o = pf_w32(buf, o, pf_jal(RV_X0, halt_off - o)) 147 pos_out[0] = o // FAIL 148 o = pf_emit_str(buf, o, "X" as *u8, 1) 149 o = pf_w32(buf, o, pf_jal(RV_X0, halt_off - o)) 150 pos_out[2] = o // HANDLER (mtvec target) 151 o = pf_emit_str(buf, o, "PF" as *u8, 2) 152 o = pf_w32(buf, o, pf_jal(RV_X0, halt_off - o)) 153 pos_out[1] = o // HALT 154 o = pf_li32(buf, o, RV_T5, PF_FIN) 155 o = pf_li32(buf, o, RV_T1, PF_PASS) 156 o = pf_w32(buf, o, pf_store(RV_T1, RV_T5, 2, 0)) 157 o = pf_w32(buf, o, pf_jal(RV_X0, 0)) 158 return o 159} 160 161func pf_parse_num(s: *u8) -> i64 { 162 var q: i64 = 0; var val: i64 = 0 163 if s[0] == (48 as u8) { if s[1] == (120 as u8) { 164 q = 2 165 var go: i64 = 1 166 while go == 1 { let c: i64 = s[q] as i64; var d: i64 = 0-1; if c>=48 { if c<=57 { d=c-48 } } if c>=97 { if c<=102 { d=c-87 } } if c>=65 { if c<=70 { d=c-55 } } if d<0 { go=0 } else { val=val*16+d; q=q+1 } } 167 return val 168 }} 169 var go2: i64 = 1 170 while go2 == 1 { let c: i64 = s[q] as i64; if c>=48 { if c<=57 { val=val*10+(c-48); q=q+1 } else { go2=0 } } else { go2=0 } } 171 return val 172} 173 174func main(argc: i64, argv: *i64) -> i64 { 175 var unmap_va: i64 = PF_VA_UNMAP 176 var outp: *u8 = PF_OUT 177 if argc >= 2 { unmap_va = pf_parse_num(argv[1] as *u8) } // gate control: pass a MAPPED VA -> no fault 178 if argc >= 3 { outp = argv[2] as *u8 } 179 let scratch: *u8 = sys_mmap(PF_MAGIC_8192) 180 let pos: *i64 = sys_mmap(32) as *i64 181 pf_emit_image(scratch, 0, 0, 0, pos, unmap_va, 0) // measure -> FAIL/HALT/HANDLER/CONT offsets 182 let fail_off: i64 = pos[0] 183 let halt_off: i64 = pos[1] 184 let handler_off: i64 = pos[2] 185 let cont_off: i64 = pos[3] 186 let buf: *u8 = sys_mmap(PF_MAGIC_8192) 187 let sz: i64 = pf_emit_image(buf, fail_off, halt_off, handler_off, pos, unmap_va, cont_off) 188 let fd: i64 = sys_openat_wr(outp, 420) 189 if fd < 0 { pf_p("PAGEFAULTEMIT verdict=RED reason=out-unwritable\n" as *u8); return 1 } 190 sys_write(fd, buf, sz); sys_close(fd) 191 let gold: *u8 = sys_mmap(8) 192 gold[0]=79 as u8; gold[1]=75 as u8; gold[2]=80 as u8; gold[3]=70 as u8 // "OKPF" 193 let gfd: i64 = sys_openat_wr(PF_GOLD, 420) 194 if gfd >= 0 { sys_write(gfd, gold, 4); sys_close(gfd) } 195 pf_p("PAGEFAULTEMIT name=" as *u8); pf_p(outp); pf_p(" bytes=" as *u8); pf_fn(1, sz); pf_p(" golden=OKPF handler@0x" as *u8); pf_fn(1, PF_MEM_BASE + handler_off); pf_p("\n" as *u8) 196 let lf: i64 = sys_openat_append(PF_LOG, 420) 197 if lf >= 0 { var n: i64=0; let m: *u8="PAGEFAULTEMIT authored _pagefault_virt.bin golden=OKPF\n" as *u8; while m[n]!=(0 as u8){n=n+1} sys_write(lf,m,n); sys_close(lf) } 198 return 0 199}