code wiki / _hdl_build / nx_pattern_emit5_register.nx
`nx_pattern_emit5_register.nx` source

1// nx_pattern_emit5_register.nx -- records GEOMETRY + PID_LOOP emitters = the pattern library's LAST two
2// shapes. Builder coverage: 10/10 (9 emitters + team-owned SCAFFOLD) -- every module shape the session
3// catalog names is now authorable hands-off, bp_claude_touch=0 for covered cores. Registered through
4// the Librarian: allocated idx + dual-write. Engineer gate = both authored tests green. license_tier: ORIGINAL
5import "nx_cap_register.nx"
6import "nx_capreg_librarian.nx"
7import "nx_syscalls.nx"
8
9func pe5r_run(path: *u8) -> i64 {
10    let pid: i64 = sys_fork()
11    if pid == 0 {
12        let dn: i64 = sys_openat_wr("/dev/null" as *u8, 0x1a4)
13        if dn >= 0 { sys_dup3(dn, 1, 0); sys_dup3(dn, 2, 0) }
14        let argv: *i64 = sys_mmap(32) as *i64; argv[0] = path as i64; argv[1] = 0
15        let envp: *i64 = sys_mmap(16) as *i64; envp[0] = 0
16        sys_execve(path, argv, envp); sys_exit(127)
17    }
18    let st: *i64 = sys_mmap(16) as *i64
19    sys_wait4(pid, st, 0)
20    return st[0]
21}
22
23func main() -> i64 {
24    var allok: i64 = 1
25    if pe5r_run("/tmp/_pe_mask_test.sov.elf" as *u8) != 0 { allok = 0 }
26    if pe5r_run("/tmp/_pe_heat_test.sov.elf" as *u8) != 0 { allok = 0 }
27    cr_w(1, "ENGINEER: team-authored geometry+pid tests all-pass=" as *u8); cr_wn(1, allok); cr_w(1, "\n" as *u8)
28    let eng: i64 = ig_engineer(1, 1, 1, allok)
29    let dec: i64 = ig_decision(eng, ig_council(eng, 1, 1, 2), 1)
30    if dec != IG_INGEST { cr_w(1, "HELD\n" as *u8); sys_exit(1) }
31    if cr_can_register(5, 2, 6, dec) != 1 { cr_w(1, "REFUSED\n" as *u8); sys_exit(1) }
32    let lp: *u8 = "/tmp/nishi_cap_registry.log" as *u8
33    let jp: *u8 = "knowledge/status/cap_registry_durable.log" as *u8
34    let idx: i64 = cl_next_idx(lp, jp)
35    let ok: i64 = cl_register_dual(lp, jp, idx, 5,
36        2, "SELF PATTERN-EMIT-5 (Builder authors GEOMETRY + PID_LOOP, shapes 9+10) -- PATTERN LIBRARY 10/10 HANDS-OFF (9 emitters + team-owned SCAFFOLD): every cataloged module shape is now team-authorable, zero Claude core logic. GEOMETRY: nm-domain area/spacing/DRC with design rules as spec params (authored _pe_mask at the REAL 5um/10um DIY-silicon floor; boundary KATs at exactly-min-feat / one-nm-under). PID_LOOP: integer PI with the PLANT SIM AS ORACLE -- emitter simulates the closed loop at emit time, REFUSES non-converging gains (dead-gains refusal PROVEN in the demo), bakes the exact endpoint as a bit-exact replay KAT (authored _pe_heat kp=2000 ki=20: settled 1027/1000 in 60 steps, clamp KAT held). ENGINEER verified all green. Registered via Librarian alloc+dual-write. Completes emit(231)/emit2(235)/emit3(241)/emit4(262)" as *u8)
37    if ok != 1 { cr_w(1, "DUAL-WRITE FAILED\n" as *u8); sys_exit(1) }
38    cr_w(1, "CAPREG idx=" as *u8); cr_wn(1, idx); cr_w(1, " REGISTERED -- PATTERN LIBRARY 10/10 SHAPES HANDS-OFF\n" as *u8)
39    sys_exit(0)
40    return 0
41}
nx_pattern_emit5_register.nx source

`nx_pattern_emit5_register.nx` source
