code wiki / _hdl_build / nx_pattern_emit7_register.nx
`nx_pattern_emit7_register.nx` source

1// nx_pattern_emit7_register.nx -- records WIRE_TLV (shape 12) + the first head-to-head autonomy
2// race verdict. Engineer gate = the authored _pe_tlv test green. Registered through the Librarian:
3// allocated idx + dual-write (the collision fix). license_tier: ORIGINAL
4import "nx_cap_register.nx"
5import "nx_capreg_librarian.nx"
6import "nx_syscalls.nx"
7
8func pe7r_run(path: *u8) -> i64 {
9    let pid: i64 = sys_fork()
10    if pid == 0 {
11        let dn: i64 = sys_openat_wr("/dev/null" as *u8, 0x1a4)
12        if dn >= 0 { sys_dup3(dn, 1, 0); sys_dup3(dn, 2, 0) }
13        let argv: *i64 = sys_mmap(32) as *i64; argv[0] = path as i64; argv[1] = 0
14        let envp: *i64 = sys_mmap(16) as *i64; envp[0] = 0
15        sys_execve(path, argv, envp); sys_exit(127)
16    }
17    let st: *i64 = sys_mmap(16) as *i64
18    sys_wait4(pid, st, 0)
19    return st[0]
20}
21
22func main() -> i64 {
23    var allok: i64 = 1
24    if pe7r_run("/tmp/pt.elf" as *u8) != 0 { allok = 0 }
25    cr_w(1, "ENGINEER: team-authored wire-tlv test pass=" as *u8); cr_wn(1, allok); cr_w(1, "\n" as *u8)
26    let eng: i64 = ig_engineer(1, 1, 1, allok)
27    let dec: i64 = ig_decision(eng, ig_council(eng, 1, 1, 2), 1)
28    if dec != IG_INGEST { cr_w(1, "HELD\n" as *u8); sys_exit(1) }
29    if cr_can_register(5, 2, 6, dec) != 1 { cr_w(1, "REFUSED\n" as *u8); sys_exit(1) }
30    let lp: *u8 = "/tmp/nishi_cap_registry.log" as *u8
31    let jp: *u8 = "knowledge/status/cap_registry_durable.log" as *u8
32    let idx: i64 = cl_next_idx(lp, jp)
33    let ok: i64 = cl_register_dual(lp, jp, idx, 5,
34        2, "SELF PATTERN-EMIT-7 WIRE_TLV (shape 12, the browser-grade binary parser) + FIRST HEAD-TO-HEAD AUTONOMY RACE: TEAM-MATCHES 1000v1000. Emitter authors [type][len][body] wire walkers from 3 spec params (type_w/len_w 1-2-4, type_first TLS-vs-PNG order; offsets baked at emit time, rule 11); count refuses truncation (-1), find returns body offset; test KATs computed from the spec; bad-width and bad-order specs REFUSED (rails proven). RACE (assignment = ClientHello extension census, B2 first half): TEAM lane = emitter-authored _pe_tlv core (ZERO Claude walk logic) vs CLAUDE lane = handwritten single-pass walk; REFEREE gate nx_ch_census_race_gate, 12 rows/lane (5 real-block offsets vs SHIPPED tls13_ext_find oracle + truncation refusal + empty-list), byte-identical staged inputs (nx_ch_census_race_stage, the REAL emitted CH for example.com, ext block 108B). VERDICT: 12/12 vs 12/12 = TEAM-MATCHES (durable knowledge/status/race_ch_census.log) -- the team now MATCHES Claude on covered-shape cores. MEASURED remaining Claude touch = the gaps to grow past: (a) STRUCT_WALK decomposition (the stager's CH fixed+var field walk to FIND the ext block -- emitter candidate), (b) IO-contract lane boilerplate (read-input/call-core/print-keys -- scaffold extension), (c) the race harness itself (stager+referee = a reusable RACE shape). Extends emit chain 231/235/241/262/264/emit6-MATH_KERNEL" as *u8)
35    if ok != 1 { cr_w(1, "DUAL-WRITE FAILED\n" as *u8); sys_exit(1) }
36    cr_w(1, "CAPREG idx=" as *u8); cr_wn(1, idx); cr_w(1, " REGISTERED -- WIRE_TLV + RACE TEAM-MATCHES 1000v1000\n" as *u8)
37    sys_exit(0)
38    return 0
39}
nx_pattern_emit7_register.nx source

`nx_pattern_emit7_register.nx` source
