code wiki / _hdl_build / nx_pattern_emit_fabricnetlist.nx
nx_pattern_emit_fabricnetlist.nx source
↩ module page · 54 lines · 3932 B
1// nx_pattern_emit_fabricnetlist.nx -- PATTERN EMITTER: FABRIC_NETLIST (shape 25, the LAST of the session's backlog).
2// Authors a gate-level FABRIC BUILDER core: emits a W-bit per-bit LUT4 fabric (W cells, each a baked LUT over a_i,b_i)
3// in the nx_fpga_fabric bitstream layout (inits + 4 src nets + po). This is the foundational fabric shape (cells+nets);
4// the authored fabric runs on the team-owned fab_eval. Completes the 5-emitter autonomy backlog. TEAM-AUTHORABLE
5// hands-off (author=emitter, no Claude logic).
6// spec[0]=W (1..32 lanes) spec[1]=lut (the per-bit 16-bit LUT4 truth table)
7// Authored fn: <name>_build(inits: *i64, src: *i64, po: *i64) -> i64 (fills the fabric; returns npi=2*W)
8// EMIT-TIME RAILS: W outside 1..32 -> REFUSED, nothing written. license_tier: ORIGINAL
9import "nx_syscalls.nx"
10
11func pfn_w(fd: i64, s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(fd, s, n); return 0 }
12func pfn_wn(fd: i64, v: i64) -> i64 { let bb: *u8=sys_mmap(28); var m: i64=v; if m<0{m=0-m; sys_write(fd,"-" as *u8,1)} let t: *u8=sys_mmap(28); var k: i64=0; if m==0{t[0]=48 as u8;k=1} while m>0{t[k]=(48+(m%10)) as u8;m=m/10;k=k+1} var i: i64=0; while i<k{bb[i]=t[k-1-i];i=i+1} sys_write(fd,bb,k); return 0 }
13
14func pfn_spec_ok(spec: *i64) -> i64 {
15 let w: i64=spec[0]
16 if w < 1 { return 0 }
17 if w > 32 { return 0 }
18 return 1
19}
20
21func pe_fn_emit_core(fd: i64, name: *u8, spec: *i64) -> i64 {
22 let w: i64=spec[0]; let lut: i64=spec[1]
23 pfn_w(fd, "// AUTHORED BY THE NISHI BUILDER (pattern: FABRIC_NETLIST) -- a W-bit per-bit LUT4 fabric, no Claude logic\n" as *u8)
24 pfn_w(fd, "func " as *u8); pfn_w(fd, name); pfn_w(fd, "_build(inits: *i64, src: *i64, po: *i64) -> i64 {\n" as *u8)
25 pfn_w(fd, " let npi: i64=" as *u8); pfn_wn(fd, 2*w); pfn_w(fd, "\n var i: i64=0\n while i<" as *u8); pfn_wn(fd, w); pfn_w(fd, " {\n" as *u8)
26 pfn_w(fd, " inits[i]=" as *u8); pfn_wn(fd, lut); pfn_w(fd, "\n" as *u8)
27 pfn_w(fd, " src[i*4+0]=i; src[i*4+1]=" as *u8); pfn_wn(fd, w); pfn_w(fd, "+i; src[i*4+2]=i; src[i*4+3]=i\n" as *u8)
28 pfn_w(fd, " po[i]=npi+i\n i=i+1\n }\n return npi\n}\n" as *u8)
29 return 1
30}
31
32// author the test: build the fabric, run it on the team-owned fab_eval with a_0=1,b_0=1, check po[0] == (lut>>15)&1
33func pe_fn_emit_test(fd: i64, name: *u8, spec: *i64) -> i64 {
34 let w: i64=spec[0]; let lut: i64=spec[1]
35 let po0: i64=(lut >> 15) & 1
36 pfn_w(fd, "import \"" as *u8); pfn_w(fd, name); pfn_w(fd, ".nx\"\nimport \"nx_fpga_fabric.nx\"\nimport \"nx_syscalls.nx\"\n" as *u8)
37 pfn_w(fd, "func main() -> i64 {\n" as *u8)
38 pfn_w(fd, " let inits: *i64=sys_mmap(" as *u8); pfn_wn(fd, 8*(w+4)); pfn_w(fd, ") as *i64; let src: *i64=sys_mmap(" as *u8); pfn_wn(fd, 8*(4*w+16)); pfn_w(fd, ") as *i64; let po: *i64=sys_mmap(" as *u8); pfn_wn(fd, 8*(w+4)); pfn_w(fd, ") as *i64\n" as *u8)
39 pfn_w(fd, " let npi: i64=" as *u8); pfn_w(fd, name); pfn_w(fd, "_build(inits, src, po)\n" as *u8)
40 pfn_w(fd, " let pi: *i64=sys_mmap(" as *u8); pfn_wn(fd, 8*(2*w+4)); pfn_w(fd, ") as *i64; let co: *i64=sys_mmap(" as *u8); pfn_wn(fd, 8*(w+4)); pfn_w(fd, ") as *i64\n" as *u8)
41 pfn_w(fd, " pi[0]=1; pi[" as *u8); pfn_wn(fd, w); pfn_w(fd, "]=1\n" as *u8)
42 pfn_w(fd, " fab_eval(" as *u8); pfn_wn(fd, w); pfn_w(fd, ", npi, inits, src, pi, co)\n" as *u8)
43 pfn_w(fd, " if fab_po(po[0], npi, pi, co) == " as *u8); pfn_wn(fd, po0); pfn_w(fd, " { sys_exit(0) }\n sys_exit(1)\n return 1\n}\n" as *u8)
44 return 1
45}
46
47func pe_fn_author(name: *u8, modpath: *u8, testpath: *u8, spec: *i64) -> i64 {
48 if pfn_spec_ok(spec) != 1 { return 0 }
49 let mf: i64=sys_openat_wr(modpath, 0x1a4); if mf < 0 { return 0 }
50 pe_fn_emit_core(mf, name, spec); sys_close(mf)
51 let tf: i64=sys_openat_wr(testpath, 0x1a4); if tf < 0 { return 0 }
52 pe_fn_emit_test(tf, name, spec); sys_close(tf)
53 return 1
54}