nx_precision_register.nx source

1// nx_precision_register.nx -- GOVERNED registration of the sub-um precision substrate 2// (nx_micron_geom + nx_metrology, gated by nx_precision_test) AND the Researcher's chip-fab arc 3// (nx_research_chipfab, gated by nx_research_chipfab_test). Two CAPREG lines, each gated on a REAL 4// re-run of its test ELF. license_tier: ORIGINAL 5import "nx_cap_register.nx" 6import "nx_syscalls.nx" 7 8const QR_NLAYERS: i64 = 6 9 10func qr_run_status(path: *u8) -> i64 { 11 let pid: i64 = sys_fork() 12 if pid == 0 { 13 let dn: i64 = sys_openat_wr("/dev/null" as *u8, 0x1a4) 14 if dn >= 0 { sys_dup3(dn, 1, 0); sys_dup3(dn, 2, 0) } 15 let argv: *i64 = sys_mmap(32) as *i64; argv[0] = path as i64; argv[1] = 0 16 let envp: *i64 = sys_mmap(16) as *i64; envp[0] = 0 17 sys_execve(path, argv, envp); sys_exit(127) 18 } 19 let st: *i64 = sys_mmap(16) as *i64 20 sys_wait4(pid, st, 0) 21 return st[0] 22} 23 24// register one cap gated on its test elf; returns 1 if registered 25func qr_reg(elf: *u8, idx: i64, layer: i64, name: *u8) -> i64 { 26 let probe: i64 = sys_openat_rd(elf) 27 var present: i64 = 0 28 if probe >= 0 { present = 1; sys_close(probe) } 29 let raw: i64 = qr_run_status(elf) 30 var ran_no_signal: i64 = 0 31 if (raw % 128) == 0 { ran_no_signal = 1 } 32 var exit_ok: i64 = 0 33 if raw == 0 { exit_ok = 1 } 34 let eng: i64 = ig_engineer(present, present, ran_no_signal, exit_ok) 35 let council: i64 = ig_council(eng, 1, 1, 2) 36 let decision: i64 = ig_decision(eng, council, 1) 37 cr_w(1, " gate raw=" as *u8); cr_wn(1, raw); cr_w(1, " decision=" as *u8); cr_wn(1, decision); cr_w(1, "\n" as *u8) 38 if decision != IG_INGEST { return 0 } 39 if cr_can_register(layer, 2, QR_NLAYERS, decision) != 1 { return 0 } 40 let fd: i64 = sys_openat_append("/tmp/nishi_cap_registry.log" as *u8, 0x1a4) 41 cr_write_entry(fd, idx, layer, name, 2) 42 sys_close(fd) 43 cr_w(1, " CAPREG idx=" as *u8); cr_wn(1, idx); cr_w(1, " REGISTERED\n" as *u8) 44 return 1 45} 46 47func main() -> i64 { 48 qr_reg("/tmp/nx_precision_test.sov.elf" as *u8, 214, 2, 49 "GEN PRECISION SUBSTRATE (shared printer+chip-fab) -- nx_micron_geom: NANOMETER fixed-point coord kernel (1 unit=1nm, plastic bracket to 5nm gate in one number system) + ppm scale calibration + step-resolution/addressability; nx_metrology: ACCURACY GATE max-deviation/mean-offset/scale-ppm + RESOLUTION CLASS (FDM/FINE/MICRON/SUBMICRON) + can_make(feature) = the honest CPU gate (only SUBMICRON makes transistors); 9/9 KATs" as *u8) 50 qr_reg("/tmp/nx_research_chipfab_test.sov.elf" as *u8, 215, 3, 51 "VER RESEARCHER chip-fab arc -- the TEAM owns the lithography/CPU-fab research (not a Claude workflow): composes nx_researcher_deep corroboration (>=2 sources + cataloged) over our verified fab corpus -> 6/8 facts ADMITTED (Zeloof Z2 10um, HackerFab 952tr 5um, open tool stack, fully-printed-CPU infeasible=litho path, hybrid FHE), 2 flagged for live pursuit (BOM $, consumables); grounded=spec-buildable; live-fetch hook wired to nx_browse_text for NAS-side egress; 4/4 KATs" as *u8) 52 sys_exit(0) 53 return 0 54}