nx_ribosome.nx source

1// nx_ribosome.nx -- target-ISA decision metadata. 2// 3// Biological analogue: a ribosome translates messenger RNA into the 4// specific protein its codons encode. Nishi ribosome is the 5// NishiLang-side decision primitive that names WHICH of the existing 6// nxc2 codegen backends should emit a call site's binary. The actual 7// codegen lives in C (aarch64.c, armv7a.c, cortex_m.c, gcn.c, 8// loongarch64.c, metal.c, mips64.c, ppc64le.c, ptx.c, riscv.c, 9// riscv32.c, s390x.c, wasm.c, x86_64.c). This primitive's job is to 10// say "this site -> emit AARCH64 NEON" or "this site -> ESP32 Xtensa" 11// based on observed heat from nx_metabolism + the cell's tropism. 12// 13// THIS IS WHAT MAKES DOOM-ON-PREGNANCY-TEST PHYSICALLY POSSIBLE: 14// the same .nx source compiles down to CORTEX_M Thumb on $5 silicon 15// (T1) and to PTX on a 5090 (T5). One IR, fourteen targets, decided 16// per call site by ribosome. 17// 18// Composes: 19// nx_tier -- NX_TIER_MCU..NX_TIER_HPC informs target choice 20// nx_metabolism -- hot sites get SIMD/GPU/SILICON targets 21// nx_pathway -- cell-spec declares preferred ribosome target 22// nx_tropism -- LOCAL_GPU tropism selects GPU-family targets 23// 24// V1 ships a sealed enum + a picker. The handoff to nxc2 is via the 25// target tag on each call site; the nxc2 main loop already reads 26// per-site target hints (see nxc2/main.c). What was missing in 27// NishiLang was the decision primitive; here it is. 28// 29// Gap list (V1 honest perf verdict): 30// - SILICON_HDL emit target is a stub (HDL backend queued) 31// - no online learning -- picker is fully deterministic 32// - no per-cell override (uses pathway-level declaration) 33// - no cross-target ABI shim (caller must keep i64/i32 alignment 34// constant; nx_tier's nx_int alias is the single tuning knob) 35// 36// genealogy_id: nishi_cardinal_2026-05-17_pathway_tropism + biology_protein_synthesis 37// lineage_id: substrate_ribosome_v1 38// 39// nx_safety_envelope: 40// intended_use: "Per-call-site target ISA decision metadata 41// consumed by the nxc2 codegen backends" 42// sil_target: SIL2 43// asil_target: QM 44// evidence: [enum_sealed, deterministic_picker, 45// 14_backends_match_existing_nxc2_set] 46// verdict: NOT_YET_EVALUATED 47 48import "nx_syscalls.nx" 49import "nx_tier.nx" 50import "nx_metabolism.nx" 51const NX_MAGIC_1024: i64 = 1024 52const NX_MAGIC_1536: i64 = 1536 53const NX_MAGIC_8192: i64 = 8192 54const NX_MAGIC_1126: i64 = 1126 55const NX_MAGIC_1228: i64 = 1228 56 57// ===== Sealed enum: NxRibosomeTarget ============================== 58// 59// Order matches nxc2's existing backend table in alphabetic order 60// of the C file name, except SILICON_HDL appended at the end. 61 62const NX_RBT_X86_64: nx_int = 0 63const NX_RBT_AARCH64: nx_int = 1 64const NX_RBT_ARMV7A: nx_int = 2 65const NX_RBT_CORTEX_M: nx_int = 3 66const NX_RBT_RISCV64: nx_int = 4 67const NX_RBT_RISCV32: nx_int = 5 68const NX_RBT_MIPS64: nx_int = 6 69const NX_RBT_PPC64LE: nx_int = 7 70const NX_RBT_LOONGARCH64: nx_int = 8 71const NX_RBT_S390X: nx_int = 9 72const NX_RBT_WASM: nx_int = 10 73const NX_RBT_PTX: nx_int = 11 // NVIDIA GPU 74const NX_RBT_GCN: nx_int = 12 // AMD GPU 75const NX_RBT_METAL: nx_int = 13 // Apple GPU 76const NX_RBT_SILICON_HDL: nx_int = 14 // Nishi sovereign silicon 77const NX_RBT_N_TARGETS: nx_int = 15 78 79// ===== Sealed enum: NxRibosomeFamily ============================== 80// 81// Higher-level grouping the picker uses; convertible to a concrete 82// NxRibosomeTarget at the call site once host detection runs. 83 84const NX_RBF_CPU: nx_int = 0 85const NX_RBF_GPU: nx_int = 1 86const NX_RBF_MCU: nx_int = 2 87const NX_RBF_WASM: nx_int = 3 88const NX_RBF_SILICON: nx_int = 4 89const NX_RBF_N_FAMILIES: nx_int = 5 90 91// ===== nx_rbt_is_valid =========================================== 92 93func nx_rbt_is_valid(t: nx_int) -> nx_int { 94 if t < 0 { return 0 } 95 if t >= NX_RBT_N_TARGETS { return 0 } 96 return 1 97} 98 99// ===== nx_rbt_family ============================================= 100// 101// Which family this target belongs to. Used by the picker to 102// promote/demote based on metabolism heat without needing to know 103// the host's specific CPU/GPU model. 104 105func nx_rbt_family(t: nx_int) -> nx_int { 106 if t == NX_RBT_CORTEX_M { return NX_RBF_MCU } 107 if t == NX_RBT_PTX { return NX_RBF_GPU } 108 if t == NX_RBT_GCN { return NX_RBF_GPU } 109 if t == NX_RBT_METAL { return NX_RBF_GPU } 110 if t == NX_RBT_WASM { return NX_RBF_WASM } 111 if t == NX_RBT_SILICON_HDL { return NX_RBF_SILICON } 112 return NX_RBF_CPU 113} 114 115// ===== nx_rbt_is_cpu ============================================= 116 117func nx_rbt_is_cpu(t: nx_int) -> nx_int { 118 if nx_rbt_family(t) == NX_RBF_CPU { return 1 } 119 return 0 120} 121 122// ===== nx_rbt_is_gpu ============================================= 123 124func nx_rbt_is_gpu(t: nx_int) -> nx_int { 125 if nx_rbt_family(t) == NX_RBF_GPU { return 1 } 126 return 0 127} 128 129// ===== nx_ribosome_default_for_tier ============================== 130// 131// Coarse default target for each tier in nx_tier. Caller's host- 132// detection layer overrides with the concrete host ISA when known; 133// this function gives ribosome a baseline so cold call sites have 134// SOMETHING to emit before metabolism has observed enough hits. 135 136func nx_ribosome_default_for_tier(tier: nx_int) -> nx_int { 137 if tier == NX_TIER_MCU { return NX_RBT_CORTEX_M } 138 if tier == NX_TIER_SOVEREIGN_CHIP { return NX_RBT_SILICON_HDL } 139 if tier == NX_TIER_FAMILY_DEVICE { return NX_RBT_AARCH64 } 140 if tier == NX_TIER_WORKSTATION { return NX_RBT_X86_64 } 141 if tier == NX_TIER_SERVER { return NX_RBT_X86_64 } 142 if tier == NX_TIER_HPC { return NX_RBT_PTX } 143 return NX_RBT_X86_64 144} 145 146// ===== nx_ribosome_pick ========================================== 147// 148// THE picker. Given the cell's tier + a metabolism profile + an 149// optional pathway-declared preference, returns the target ISA the 150// nxc2 codegen layer should emit for this site. 151// 152// Argument contract: 153// tier -- nx_tier_* 154// m -- *NxMetabolism (NULL OK; treated as cold-site default) 155// site_id -- profiler key 156// prefer -- pathway-declared target hint; NX_RBT_N_TARGETS means "no preference" 157// 158// Decision precedence: 159// 1. pathway preference if explicitly valid 160// 2. metabolism-suggested tier overrides the cold-site default 161// 3. cold-site default for the cell's current tier 162 163func nx_ribosome_pick(tier: nx_int, 164 m: *NxMetabolism, 165 site_id: nx_int, 166 prefer: nx_int) -> nx_int { 167 if nx_rbt_is_valid(prefer) == 1 { return prefer } 168 169 var effective_tier: nx_int = tier 170 if (m as i64) != 0 { 171 let suggested: nx_int = nx_metab_suggest_target(m, site_id) 172 if suggested > effective_tier { effective_tier = suggested } 173 } 174 return nx_ribosome_default_for_tier(effective_tier) 175} 176 177// ===== nx_ribosome_cost_q10 ====================================== 178// 179// Coarse instructions-per-equivalent-x86-op estimate. Used by the 180// pathway-level cost model to compare placement options. Q10 unity = 181// equal to x86_64 baseline. Higher = slower per-op; lower = faster. 182// CORTEX_M is slower per op but vastly lower power; PTX has gather 183// op overhead vs sequential x86 for non-bulk kernels. 184 185func nx_ribosome_cost_q10(t: nx_int) -> nx_int { 186 if t == NX_RBT_X86_64 { return NX_MAGIC_1024 } 187 if t == NX_RBT_AARCH64 { return NX_MAGIC_1024 } 188 if t == NX_RBT_ARMV7A { return NX_MAGIC_1536 } 189 if t == NX_RBT_CORTEX_M { return NX_MAGIC_8192 } 190 if t == NX_RBT_RISCV64 { return NX_MAGIC_1126 } 191 if t == NX_RBT_RISCV32 { return NX_MAGIC_1228 } 192 if t == NX_RBT_MIPS64 { return NX_MAGIC_1228 } 193 if t == NX_RBT_PPC64LE { return NX_MAGIC_1024 } 194 if t == NX_RBT_LOONGARCH64 { return NX_MAGIC_1024 } 195 if t == NX_RBT_S390X { return NX_MAGIC_1024 } 196 if t == NX_RBT_WASM { return NX_MAGIC_1536 } 197 if t == NX_RBT_PTX { return 512 } 198 if t == NX_RBT_GCN { return 512 } 199 if t == NX_RBT_METAL { return 512 } 200 if t == NX_RBT_SILICON_HDL { return 64 } 201 return NX_MAGIC_1024 202}