nx_room_l4s_gate.nx source
↩ module page · 140 lines · 7632 B
1// nx_room_l4s_gate.nx -- LIVE GATE for the L4S dual-signal congestion controller.
2// Proves the cross-path robustness exceed: ONE controller (react to ECN mark OR delay
3// setpoint) stays latency-bounded across BOTH an ECN-capable bottleneck AND a dumb-FIFO
4// (non-ECN) bottleneck -- where each SINGLE signal fails on one of the two paths.
5//
6// the two path types x the controllers:
7// A = L4S dual on ECN-capable path -> tight (ECN arm dominates, ~K)
8// B = L4S dual on dumb-FIFO path -> bounded (delay arm holds, ~KD)
9// Ce = ECN-only on ECN-capable path -> fine (its native path)
10// Cf = ECN-only on dumb-FIFO path -> BLOAT (BLIND: never marks) <- the gap L4S closes
11// Dd = delay-only on ECN-capable path -> looser (no explicit mark, sits at KD)
12//
13// criteria:
14// 1 A util >= 90% (L4S keeps the ECN link full)
15// 2 A q_p99 <= 3*K (L4S TIGHT on the ECN path)
16// 3 B util >= 90% (L4S keeps the FIFO link full)
17// 4 B q_p99 <= 3*KD (L4S BOUNDED on the FIFO path = graceful)
18// 5 Cf q_p99 >= 3*B q_p99 (ECN-only BLOATS on FIFO -- the blind spot)
19// 6 Ce util>=90% AND Ce q_p99 <= 3*K (ECN-only is fine on its native path =>
20// the failure is PATH-SPECIFIC, not ECN broken)
21// 7 Dd q_p99 >= A q_p99 + 4 (the ECN arm genuinely TIGHTENS vs delay-only)
22// 8 telemetry error == 0 on every run (NC liar-kill: reported queue == true queue)
23//
24// expect_exit: 0 license_tier: ORIGINAL
25import "nx_room_l4s.nx"
26
27func gp(s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } sys_write(1, s, n); return 0 }
28func fw(fd: i64, s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } sys_write(fd, s, n); return 0 }
29func gn(v: i64) -> i64 {
30 let b: *u8 = sys_mmap(28); var m: i64 = v
31 if m < 0 { m = 0 - m; sys_write(1, "-" as *u8, 1) }
32 let t: *u8 = sys_mmap(28); var k: i64 = 0
33 if m == 0 { t[0] = 48 as u8; k = 1 }
34 while m > 0 { t[k] = (48 + (m % 10)) as u8; m = m / 10; k = k + 1 }
35 var i: i64 = 0
36 while i < k { b[i] = t[k - 1 - i]; i = i + 1 }
37 sys_write(1, b, k); return 0
38}
39func fn2(fd: i64, v: i64) -> i64 {
40 let b: *u8 = sys_mmap(28); var m: i64 = v; if m < 0 { m = 0 - m; sys_write(fd, "-" as *u8, 1) }
41 let t: *u8 = sys_mmap(28); var k: i64 = 0
42 if m == 0 { t[0] = 48 as u8; k = 1 }
43 while m > 0 { t[k] = (48 + (m % 10)) as u8; m = m / 10; k = k + 1 }
44 var i: i64 = 0
45 while i < k { b[i] = t[k - 1 - i]; i = i + 1 }
46 sys_write(fd, b, k); return 0
47}
48func chk(name: *u8, ok: i64) -> i64 {
49 if ok == 1 { gp(" PASS " as *u8); gp(name); gp("\n" as *u8); return 1 }
50 gp(" FAIL " as *u8); gp(name); gp("\n" as *u8); return 0
51}
52func show(tag: *u8, m: *CcMetrics) -> i64 {
53 gp(tag); gp(": util(x1000)=" as *u8); gn(m.util_x1000); gp(" q_p50=" as *u8); gn(m.q_p50)
54 gp(" q_p99=" as *u8); gn(m.q_p99); gp(" drops=" as *u8); gn(m.drops)
55 gp(" tele_err=" as *u8); gn(m.tele_max_err); gp(" ticks=" as *u8); gn(m.ticks); gp("\n" as *u8); return 0
56}
57
58func main() -> i64 {
59 let N: i64 = 1200
60 let D: i64 = 4
61 let RTT: i64 = 8 // BDP = 32
62 let BUF: i64 = 200
63 let K: i64 = 16 // ECN setpoint (tight, explicit)
64 let KD: i64 = 40 // delay setpoint (looser, implicit)
65 let OPENW: i64 = 170 // all modes START bloated; must drive down
66
67 gp("nx_room_l4s gate -- L4S dual-signal (ECN OR delay) congestion control, cross-path\n" as *u8)
68 gp("link: N=" as *u8); gn(N); gp(" drain=" as *u8); gn(D); gp("/tick RTT=" as *u8); gn(RTT)
69 gp(" (BDP=" as *u8); gn(D * RTT); gp(") buffer=" as *u8); gn(BUF)
70 gp(" ECN-K=" as *u8); gn(K); gp(" delay-KD=" as *u8); gn(KD); gp("\n" as *u8)
71
72 let a: *CcMetrics = sys_mmap(64) as *CcMetrics
73 let b: *CcMetrics = sys_mmap(64) as *CcMetrics
74 let ce: *CcMetrics = sys_mmap(64) as *CcMetrics
75 let cf: *CcMetrics = sys_mmap(64) as *CcMetrics
76 let dd: *CcMetrics = sys_mmap(64) as *CcMetrics
77
78 l4s_run(L4S_DUAL, 1, N, D, RTT, BUF, K, KD, OPENW, a) // dual, ECN path
79 l4s_run(L4S_DUAL, 0, N, D, RTT, BUF, K, KD, OPENW, b) // dual, FIFO path
80 l4s_run(L4S_ECN, 1, N, D, RTT, BUF, K, KD, OPENW, ce) // ECN-only, ECN path
81 l4s_run(L4S_ECN, 0, N, D, RTT, BUF, K, KD, OPENW, cf) // ECN-only, FIFO path -> blind
82 l4s_run(L4S_DELAY, 1, N, D, RTT, BUF, K, KD, OPENW, dd) // delay-only, ECN path
83
84 show("A L4S-dual ECN-path " as *u8, a)
85 show("B L4S-dual FIFO-path" as *u8, b)
86 show("Ce ECN-only ECN-path " as *u8, ce)
87 show("Cf ECN-only FIFO-path" as *u8, cf)
88 show("Dd delay-only ECN-path " as *u8, dd)
89
90 var pass: i64 = 0
91 var tot: i64 = 0
92
93 var c1: i64 = 0; if a.util_x1000 >= 900 { c1 = 1 }
94 pass = pass + chk("1 A util >= 90% (L4S keeps the ECN link full)" as *u8, c1); tot = tot + 1
95
96 var c2: i64 = 0; if a.q_p99 <= 3 * K { c2 = 1 }
97 pass = pass + chk("2 A q_p99 <= 3*K (L4S TIGHT on the ECN path)" as *u8, c2); tot = tot + 1
98
99 var c3: i64 = 0; if b.util_x1000 >= 900 { c3 = 1 }
100 pass = pass + chk("3 B util >= 90% (L4S keeps the FIFO link full)" as *u8, c3); tot = tot + 1
101
102 var c4: i64 = 0; if b.q_p99 <= 3 * KD { c4 = 1 }
103 pass = pass + chk("4 B q_p99 <= 3*KD (L4S BOUNDED on the FIFO path = graceful)" as *u8, c4); tot = tot + 1
104
105 var c5: i64 = 0; if b.q_p99 >= 1 { if cf.q_p99 >= 3 * b.q_p99 { c5 = 1 } }
106 pass = pass + chk("5 Cf q_p99 >= 3*B (ECN-only BLOATS on FIFO -- the blind spot L4S closes)" as *u8, c5); tot = tot + 1
107
108 var c6: i64 = 0; if ce.util_x1000 >= 900 { if ce.q_p99 <= 3 * K { c6 = 1 } }
109 pass = pass + chk("6 Ce fine on ECN path (failure is PATH-SPECIFIC, not ECN broken)" as *u8, c6); tot = tot + 1
110
111 var c7: i64 = 0; if dd.q_p99 >= a.q_p99 + 4 { c7 = 1 }
112 pass = pass + chk("7 Dd q_p99 >= A+4 (the ECN arm genuinely TIGHTENS vs delay-only)" as *u8, c7); tot = tot + 1
113
114 var c8: i64 = 0
115 if a.tele_max_err == 0 { if b.tele_max_err == 0 { if ce.tele_max_err == 0 { if cf.tele_max_err == 0 { if dd.tele_max_err == 0 { c8 = 1 } } } } }
116 pass = pass + chk("8 telemetry error == 0 every run (NC liar-kill, no fabricated queue)" as *u8, c8); tot = tot + 1
117
118 gp("---- nx_room_l4s gate: passed " as *u8); gn(pass); gp(" / " as *u8); gn(tot); gp("\n" as *u8)
119
120 if pass == tot {
121 let lfd: i64 = sys_openat_append("knowledge/status/room_l4s.log" as *u8, 0x1a4)
122 if lfd >= 0 {
123 fw(lfd, "R-L4S organ=nx_room_l4s checks=" as *u8); fn2(lfd, pass); fw(lfd, "/" as *u8); fn2(lfd, tot)
124 fw(lfd, " A_ecn_q99=" as *u8); fn2(lfd, a.q_p99); fw(lfd, " B_fifo_q99=" as *u8); fn2(lfd, b.q_p99)
125 fw(lfd, " Cf_ecnonly_fifo_q99=" as *u8); fn2(lfd, cf.q_p99); fw(lfd, " Dd_delayonly_ecn_q99=" as *u8); fn2(lfd, dd.q_p99)
126 fw(lfd, " dual-signal-bounded-across-paths+NC verdict=GREEN\n" as *u8)
127 sys_close(lfd)
128 }
129 gp("L4S LIVE GREEN -- one controller, latency BOUNDED across ECN and dumb-FIFO paths\n" as *u8)
130 sys_exit(0)
131 }
132 let rfd: i64 = sys_openat_append("knowledge/status/room_l4s.log" as *u8, 0x1a4)
133 if rfd >= 0 {
134 fw(rfd, "R-L4S organ=nx_room_l4s checks=" as *u8); fn2(rfd, pass); fw(rfd, "/" as *u8); fn2(rfd, tot)
135 fw(rfd, " verdict=RED\n" as *u8)
136 sys_close(rfd)
137 }
138 sys_exit(1)
139 return 0
140}