code wiki / _hdl_build / nx_rtype_control_mem_test.nx
nx_rtype_control_mem_test.nx source
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1// nx_rtype_control_mem_test.nx -- FUNCTIONAL gate-level verify of the R-type ALU-op control.
2// Builds nx_rtype_op_aluop_build into a MEM sink, then exhaustively over funct3 in 0..7 x funct7 in
3// {0, 1, 0x20} runs the gate-sim and diffs the alu-op net against the behavioral oracle
4// nx_rv64im_sim_alu_select(OP, funct3, funct7). All 24 combos must match. KATs: add/sub/sra/mul.
5// Proves the decode->execute control glue is correct at the gate level. Sovereign.
6// license_tier: ORIGINAL expect_exit: 0
7import "nx_rtype_control.nx"
8import "rv64im_min_sim.nx" // nx_rv64im_sim_alu_select + NX_RV64IM_OP_OP
9
10func _emit_cstr(s: *u8) -> i64 {
11 var n: i64 = 0
12 while s[n] != (0 as u8) { n = n + 1 }
13 sys_write(1, s, n)
14 return 0
15}
16func _emit_dec(v: i64) -> i64 {
17 let b: *u8 = sys_mmap(28)
18 let t2: *u8 = sys_mmap(28)
19 var n: i64 = v
20 if n < 0 { n = 0 - n }
21 var t: i64 = 0
22 if n == 0 { t2[0] = 48; t = 1 }
23 while n > 0 { t2[t] = 48 + (n % 10); n = n / 10; t = t + 1 }
24 var i: i64 = 0
25 while i < t { b[i] = t2[t - 1 - i]; i = i + 1 }
26 sys_write(1, b, t)
27 return 0
28}
29
30func main() -> i64 {
31 let cells: *NxGsimCell = sys_mmap(48 * 512) as *NxGsimCell
32 let vals: *i64 = sys_mmap(8 * 512) as *i64
33 let g: *NxGsim = sys_mmap(64) as *NxGsim
34 g.cells = cells
35 g.vals = vals
36 let k: *NxCellSink = sys_mmap(64) as *NxCellSink
37
38 g.n_nets = 2 // net 0 = funct3, net 1 = funct7
39 g.n_cells = 0
40 nx_sink_init_mem(k, g)
41 let aluop: i64 = nx_rtype_op_aluop_build(k, 0, 1)
42
43 let f7s: *i64 = sys_mmap(8 * 4) as *i64
44 f7s[0] = 0; f7s[1] = 1; f7s[2] = 32
45 var mism: i64 = 0
46 var checks: i64 = 0
47 var fi: i64 = 0
48 while fi < 3 {
49 var f3: i64 = 0
50 while f3 < 8 {
51 g.vals[0] = f3
52 g.vals[1] = f7s[fi]
53 if nx_gsim_run(g) != NX_GSIM_OK { sys_exit(40); return 40 }
54 let got: i64 = g.vals[aluop]
55 let exp: i64 = nx_rv64im_sim_alu_select(NX_RV64IM_OP_OP, f3, f7s[fi])
56 if got != exp { mism = mism + 1 }
57 checks = checks + 1
58 f3 = f3 + 1
59 }
60 fi = fi + 1
61 }
62 _emit_cstr("rtype control: checks=" as *u8); _emit_dec(checks)
63 _emit_cstr(" mismatches=" as *u8); _emit_dec(mism); _emit_cstr("\n" as *u8)
64
65 // KATs: (f3,f7) -> alu op
66 var kat_ok: i64 = 1
67 g.vals[0] = 0; g.vals[1] = 0; nx_gsim_run(g)
68 let v_add: i64 = g.vals[aluop]
69 if v_add != NX_RV64IM_ALU_ADD { kat_ok = 0 }
70 g.vals[0] = 0; g.vals[1] = 32; nx_gsim_run(g)
71 let v_sub: i64 = g.vals[aluop]
72 if v_sub != NX_RV64IM_ALU_SUB { kat_ok = 0 }
73 g.vals[0] = 5; g.vals[1] = 32; nx_gsim_run(g)
74 let v_sra: i64 = g.vals[aluop]
75 if v_sra != NX_RV64IM_ALU_SRA { kat_ok = 0 }
76 g.vals[0] = 0; g.vals[1] = 1; nx_gsim_run(g)
77 let v_mul: i64 = g.vals[aluop]
78 if v_mul != NX_RV64IM_ALU_MUL { kat_ok = 0 }
79 _emit_cstr("KATs add=" as *u8); _emit_dec(v_add)
80 _emit_cstr(" sub=" as *u8); _emit_dec(v_sub)
81 _emit_cstr(" sra=" as *u8); _emit_dec(v_sra)
82 _emit_cstr(" mul=" as *u8); _emit_dec(v_mul); _emit_cstr("\n" as *u8)
83
84 if mism != 0 { sys_exit(1); return 1 }
85 if kat_ok != 1 { sys_exit(2); return 2 }
86 _emit_cstr("R-TYPE CONTROL gate-verify PASS (24 combos 0 mismatch; add/sub/sra/mul KATs exact)\n" as *u8)
87 sys_exit(0)
88 return 0
89}