nx_rv64_kernel_gate.nx source

1// nx_rv64_kernel_gate.nx -- CAPSTONE: the sovereign emulator runs a real bare-metal KERNEL, bit-identical to QEMU. 2// Loads knowledge/hw/kernel.bin -- a gcc -march=rv64imac_zicsr compiled C kernel that COMPOSES the privileged 3// primitives a real OS uses together: mtvec trap-vector setup + a machine-timer INTERRUPT HANDLER (gcc interrupt 4// attribute: save/restore + mret) + timer re-arm + mstatus.MIE/mie.MTIE + an IDLE LOOP that advances ONLY via timer 5// interrupts (the preemptive-scheduler primitive) + deterministic disarm at N ticks. Runs it on the golden sim (full 6// privileged CPU + CLINT + UART) and confirms UART == 05 03 2a (ticks=5, handler-checksum=3, sentinel) -- which == 7// qemu-system-riscv64 (deterministic across runs). Proves the emulator runs real KERNEL code (interrupts composed), 8// not just isolated feature tests -- the foundation is ready for NishiOS-on-RISC-V kernel development. expect_exit: 0 9import "nx_syscalls.nx" 10import "nishi_hdl_primitives.nx" 11import "rv64im_min_decoder.nx" 12import "rv64im_min_alu.nx" 13import "rv64im_min_regfile.nx" 14import "rv64im_min_csr.nx" 15import "rv64im_min_clint.nx" 16import "rv64im_min_uart.nx" 17import "rv64im_min_virtio.nx" 18import "rv64im_min_mmu.nx" 19import "rv64im_min_sim.nx" 20 21func g_puts(s: *u8) -> i64 { var n: i64=0; while s[n]!=(0 as u8){n=n+1} sys_write(1,s,n); return 0 } 22func g_pn(v: i64) -> i64 { let b: *u8=sys_mmap(28); var x: i64=v; if x==0{b[0]=48;sys_write(1,b,1);return 0} var d: i64=0; var y: i64=x; while y>0{d=d+1;y=y/10} var i: i64=d-1; y=x; while i>=0{b[i]=(48+(y%10)) as u8;y=y/10;i=i-1} sys_write(1,b,d); return 0 } 23func g_hx(v: i64) -> i64 { let b: *u8=sys_mmap(4); let n0: i64=(v>>4)&15; let n1: i64=v&15; if n0<10 { b[0]=(48+n0) as u8 } else { b[0]=(87+n0) as u8 } if n1<10 { b[1]=(48+n1) as u8 } else { b[1]=(87+n1) as u8 } b[2]=32 as u8; sys_write(1,b,3); return 0 } 24func ck(name: *u8, c: i64) -> i64 { if c==1 { g_puts(" PASS " as *u8) } else { g_puts(" FAIL " as *u8) } g_puts(name); g_puts("\n" as *u8); return c } 25const DMEM_BASE: i64 = 0x80000000 26const DMEM_SIZE: i64 = 262144 27 28func main() -> i64 { 29 g_puts("nx_rv64_kernel_gate (the sovereign emulator runs a real bare-metal timer-interrupt KERNEL -- vs QEMU 05 03 2a)\n" as *u8) 30 var pass: i64=0; var total: i64=0 31 let lenbox: *i64=sys_mmap(16) as *i64 32 let code: *u8=sys_read_file("knowledge/hw/kernel.bin" as *u8, lenbox) 33 if (code as i64)==0 { g_puts(" NO kernel.bin\n" as *u8); sys_exit(1); return 1 } 34 let nb: i64=lenbox[0] 35 g_puts(" loaded kernel.bin: "); g_pn(nb); g_puts(" bytes of gcc-compiled bare-metal C (timer interrupts)\n" as *u8) 36 37 let rf_storage: *i64=sys_mmap(8*NX_RV64IM_RF_N_REGS) as *i64; let csr_storage: *i64=sys_mmap(8*NX_CSR_SLOT_N) as *i64 38 let clint_storage: *i64=sys_mmap(8*NX_CLINT_SLOT_N) as *i64; let uart_storage: *i64=sys_mmap(8*NX_UART_SLOT_N) as *i64 39 let mem: *u8=sys_mmap(DMEM_SIZE); let tx_buf: *u8=sys_mmap(256) 40 let rf: *NxRv64imRegfile=sys_mmap(64) as *NxRv64imRegfile; let csr: *NxRv64imCsrFile=sys_mmap(64) as *NxRv64imCsrFile 41 let clint: *NxClint=sys_mmap(64) as *NxClint; let uart: *NxUart=sys_mmap(64) as *NxUart; let sim: *NxRv64imSim=sys_mmap(128) as *NxRv64imSim 42 nx_rv64im_rf_init(rf, rf_storage); nx_rv64im_csr_init(csr, csr_storage, 0); nx_clint_init(clint, clint_storage); nx_uart_init(uart, uart_storage, tx_buf, 256) 43 nx_rv64im_sim_init(sim, rf, csr, clint, uart, DMEM_BASE, mem, DMEM_SIZE, 0) 44 var i: i64=0; while i<nb { mem[i]=code[i]; i=i+1 } 45 nx_rv64im_sim_run(sim, 500000000) 46 let n: i64=nx_uart_tx_count(uart) 47 g_puts(" golden sim UART ("); g_pn(n); g_puts(" bytes): "); i=0; while i<n { g_hx(tx_buf[i] as i64); i=i+1 } g_puts("\n" as *u8) 48 g_puts(" expected (== QEMU) : 05 03 2a (5 timer ticks, handler checksum 0x03, sentinel)\n" as *u8) 49 50 var t1: i64=0 51 if n==3 { if tx_buf[0]==(0x05 as u8) { if tx_buf[1]==(0x03 as u8) { if tx_buf[2]==(0x2a as u8) { t1=1 } } } } 52 pass=pass+ck("T1: the emulator runs the gcc-compiled timer-interrupt kernel -> UART = 05 03 2a (== QEMU, deterministic)" as *u8, t1); total=total+1 53 54 var okall: i64=0; if pass==total { okall=1 } 55 g_puts("---- nx_rv64_kernel_gate: passed "); g_pn(pass); g_puts(" / "); g_pn(total); g_puts(" ----\n" as *u8) 56 if okall==1 { 57 let logf: i64=sys_openat_append("knowledge/status/kernel.log" as *u8, 420) 58 if logf>=0 { let z: i64=sys_write(logf,"NXRV64KERNEL GREEN: the sovereign emulator runs a real bare-metal timer-interrupt KERNEL (gcc -march=rv64imac_zicsr: mtvec + interrupt handler + mret + re-arm + mstatus/mie + idle loop advancing only via interrupts) == QEMU 05 03 2a. the emulator runs real KERNEL code, not just isolated feature tests.\n" as *u8,320); sys_close(logf) } 59 g_puts("verdict=GREEN (the sovereign emulator runs a real bare-metal timer-interrupt kernel == QEMU -- privileged primitives COMPOSED, the foundation is ready for NishiOS-on-RISC-V kernel dev)\n" as *u8); sys_exit(0); return 0 60 } 61 g_puts("verdict=RED\n" as *u8); sys_exit(1); return 1 62}