nx_simd_sse_kat_gate.nx source

1// nx_simd_sse_kat_gate.nx -- SOVEREIGN 128-bit SSE2 vector run-KAT: the 2// FIRST rung of the sovereign VECTOR backend, proving xmm load/compute/store 3// on REAL x86 silicon (NO gcc / NO qemu / NO binutils). AUTHOR=ORGAN, no-false-green. 4// 5// What it proves: the sovereign encoder+assembler now emit CORRECT 128-bit 6// vector MEMORY load/store (nxasm_x86_enc.x86_sse_mem + the nxasm_x86 7// movdqu/movdqa K_MEM dispatch). It ASSEMBLES two tiny programs with the 8// team's own _offc/nxasm_x86_main.elf and EXECUTES the resulting ELFs: 9// POS: movdqu-load vecA=[10,0,0,0] + vecB=[32,0,0,0] (4x u32 LE); 10// paddd -> lane0 = 42; movdqu-store; reload lane0 -> exit(42). 11// NEG: identical, then pxor %xmm0,%xmm0 (zero) -> store -> exit(0). 12// GREEN iff pos==42 AND neg==0 AND pos!=neg. Distinct pos/neg => the gate 13// reads the ACTUAL silicon-computed exit, never a baked constant. This run- 14// proves FOUR encoder forms end to end: movdqu-load(NEW) + movdqu-store(NEW) 15// + paddd + pxor -- the latter two were only ever EMITTED (SHA-NI core), never 16// EXECUTED until now. Foundation for the 256-bit(VEX) / 512-bit(EVEX) rungs. 17// Writes knowledge/status/simd_vec_kat.log. license_tier: ORIGINAL 18import "nx_syscalls.nx" 19 20const ASM_TOOL: *u8 = "_offc/nxasm_x86_main.elf" 21const SV_LOG: *u8 = "knowledge/status/simd_vec_kat.log" 22 23func gw(fd: i64, s: *u8) -> i64 { var n: i64 = 0; while s[n] != (0 as u8) { n = n + 1 } sys_write(fd, s, n); return 0 } 24func gwn(fd: i64, v: i64) -> i64 { 25 let bb: *u8 = sys_mmap(28); var m: i64 = v 26 if m < 0 { m = 0 - m; sys_write(fd, "-" as *u8, 1) } 27 let t: *u8 = sys_mmap(28); var k: i64 = 0 28 if m == 0 { t[0] = 48; k = 1 } 29 while m > 0 { t[k] = (48 + (m % 10)) as u8; m = m / 10; k = k + 1 } 30 var i: i64 = 0 31 while i < k { bb[i] = t[k - 1 - i]; i = i + 1 } 32 sys_write(fd, bb, k); return 0 33} 34 35// fork + mute child stdout/stderr + execve(path, argv); parent waits; returns 36// child's WEXITSTATUS, or 128+signal if it died to a signal (a segfaulted 37// program/tool must NOT decode as a false 0). Clone of the proven sbr_run spine. 38func g_run(path: *u8, argv: *i64) -> i64 { 39 let envp: *i64 = sys_mmap(8 * 4) as *i64 40 envp[0] = "PATH=/usr/bin:/bin" as *u8 as i64 41 envp[1] = 0 42 let dn: i64 = sys_openat_wr("/dev/null" as *u8, 0x1a4) 43 let pid: i64 = sys_fork() 44 if pid == 0 { 45 if dn >= 0 { sys_dup3(dn, 1, 0) } 46 if dn >= 0 { sys_dup3(dn, 2, 0) } 47 sys_execve(path, argv, envp) 48 sys_exit(127) 49 } 50 let st: *i64 = sys_mmap(16) as *i64 51 sys_wait4(pid, st, 0) 52 if dn >= 0 { sys_close(dn) } 53 let sig: i64 = st[0] & 0x7f 54 if sig != 0 { return 128 + sig } 55 return (st[0] >> 8) & 0xff 56} 57 58// assemble spath -> elfpath with the team's sovereign assembler, then run the 59// ELF. Returns the program's exit, or 0-200-rc if the assemble step failed 60// (distinct negative => surfaces an encode gap rather than masquerading as a value). 61func asm_and_run(spath: *u8, elfpath: *u8) -> i64 { 62 let aa: *i64 = sys_mmap(8 * 4) as *i64 63 aa[0] = ASM_TOOL as i64 64 aa[1] = spath as i64 65 aa[2] = elfpath as i64 66 aa[3] = 0 67 let rc_a: i64 = g_run(ASM_TOOL, aa) 68 if rc_a != 0 { return 0 - 200 - rc_a } 69 let rr: *i64 = sys_mmap(8 * 4) as *i64 70 rr[0] = elfpath as i64 71 rr[1] = 0 72 return g_run(elfpath, rr) 73} 74 75// Emit the KAT .s. zero==1 inserts `pxor %xmm0,%xmm0` (the NEG variant). 76// RIP-relative addressing only => position-independent, base-invariant. 77func write_kat_s(path: *u8, zero: i64) -> i64 { 78 let fd: i64 = sys_openat_wr(path, 0x1a4) 79 if fd < 0 { return 0 - 1 } 80 gw(fd, ".text\n" as *u8) 81 gw(fd, "_start:\n" as *u8) 82 gw(fd, "leaq vecA(%rip), %rdi\n" as *u8) 83 gw(fd, "movdqu (%rdi), %xmm0\n" as *u8) // NEW: 128-bit mem LOAD 84 gw(fd, "leaq vecB(%rip), %rsi\n" as *u8) 85 gw(fd, "movdqu (%rsi), %xmm1\n" as *u8) 86 gw(fd, "paddd %xmm1, %xmm0\n" as *u8) // packed 32-bit add (now run-proven) 87 if zero == 1 { gw(fd, "pxor %xmm0, %xmm0\n" as *u8) } 88 gw(fd, "leaq outbuf(%rip), %rdx\n" as *u8) 89 gw(fd, "movdqu %xmm0, (%rdx)\n" as *u8) // NEW: 128-bit mem STORE 90 gw(fd, "movl (%rdx), %edi\n" as *u8) // lane0 -> exit code 91 gw(fd, "movabsq $60, %rax\n" as *u8) 92 gw(fd, "syscall\n" as *u8) 93 gw(fd, ".section .rodata\n" as *u8) 94 gw(fd, "vecA:\n" as *u8) 95 gw(fd, ".byte 10,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n" as *u8) 96 gw(fd, "vecB:\n" as *u8) 97 gw(fd, ".byte 32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0\n" as *u8) 98 gw(fd, ".lcomm outbuf, 16\n" as *u8) 99 sys_close(fd) 100 return 0 101} 102 103func g_emit(fd: i64, pos: i64, neg: i64, ok: i64) -> i64 { 104 gw(fd, "SIMD_VEC_KAT rung=R0-sse128 authored=organ width=128 reg=xmm forms=movdqu-load+movdqu-store+paddd+pxor sovereign(nx_cc->nxasm_x86,no-gcc/qemu/binutils) silicon=real pos42=" as *u8); gwn(fd, pos) 105 gw(fd, " neg0=" as *u8); gwn(fd, neg) 106 gw(fd, " distinct=" as *u8); if pos != neg { gwn(fd, 1) } else { gwn(fd, 0) } 107 if ok == 1 { gw(fd, " verdict=GREEN\n" as *u8) } else { gw(fd, " verdict=RED reason=exit-mismatch-or-encode-gap\n" as *u8) } 108 return 0 109} 110 111func main() -> i64 { 112 write_kat_s("/tmp/_sse_kat_pos.s" as *u8, 0) 113 let pos: i64 = asm_and_run("/tmp/_sse_kat_pos.s" as *u8, "/tmp/_sse_kat_pos.elf" as *u8) 114 write_kat_s("/tmp/_sse_kat_neg.s" as *u8, 1) 115 let neg: i64 = asm_and_run("/tmp/_sse_kat_neg.s" as *u8, "/tmp/_sse_kat_neg.elf" as *u8) 116 117 var ok: i64 = 1 118 if pos != 42 { ok = 0 } 119 if neg != 0 { ok = 0 } 120 if pos == neg { ok = 0 } 121 122 g_emit(1, pos, neg, ok) 123 let lf: i64 = sys_openat_append(SV_LOG, 420) 124 if lf >= 0 { g_emit(lf, pos, neg, ok); sys_close(lf) } 125 if ok == 1 { return 0 } 126 return 1 127}